公开(公告)号：US10885952B1

公开(公告)日：2021-01-05

申请号：US16727623

申请日：2019-12-26

Applicant: Cadence Design Systems, Inc.

Inventor： Sandeep Brahmadathan ,  Takashi Ueda ,  Jeffrey S. Earl ,  Utpal Mahanta

IPC: G11C8/00 ,  G11C7/10 ,  G11C7/22 ,  G06F13/16

Abstract: Various embodiments described herein provide for a data transfer mechanism for a memory device, such as a Double Data Rate (DDR) memory device, which can improve critical timing within the memory device without a latency impact. In addition, various embodiments described herein provide for a switching sequence for a memory device, which can improve switching time for the memory device.