公开(公告)号：US10885952B1

公开(公告)日：2021-01-05

申请号：US16727623

申请日：2019-12-26

Applicant: Cadence Design Systems, Inc.

Inventor： Sandeep Brahmadathan ,  Takashi Ueda ,  Jeffrey S. Earl ,  Utpal Mahanta

IPC: G11C8/00 ,  G11C7/10 ,  G11C7/22 ,  G06F13/16

Abstract: Various embodiments described herein provide for a data transfer mechanism for a memory device, such as a Double Data Rate (DDR) memory device, which can improve critical timing within the memory device without a latency impact. In addition, various embodiments described herein provide for a switching sequence for a memory device, which can improve switching time for the memory device.

公开(公告)号：US08760210B1

公开(公告)日：2014-06-24

申请号：US13626787

申请日：2012-09-25

Applicant: Cadence Design Systems, Inc.

Inventor： Jeffrey S. Earl

IPC: H03H11/26

CPC classification number: H03K5/131 ,  H03K2005/00104

Abstract: A method and system in accordance with the present invention provides for a method and circuit for oversampling using a delay element in which input clock signals and input data signals are affected by phase and time delays to provide for the circuit generating samples providing a greater granularity of detail over a period, thereby reducing error probabilities.

Abstract translation: 根据本发明的方法和系统提供了一种用于使用延迟元件进行过采样的方法和电路，其中输入时钟信号和输入数据信号受到相位和时间延迟的影响，以提供产生样本的电路，从而提供更大的粒度 细节，从而减少错误概率。