公开(公告)号：US11775719B1

公开(公告)日：2023-10-03

申请号：US17713004

申请日：2022-04-04

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Xiaopeng Dong ,  Sourabh Rajguru

IPC: G06F30/30 ,  G06F30/3315 ,  G06F119/12

CPC classification number: G06F30/3315 ,  G06F2119/12

Abstract: Various embodiments provide a charge model for a cell instance for delay calculation of a circuit design that includes the cell instance, where the charge model can be part of electronic design automation (EDA) and used in timing analysis of a circuit design that includes the cell instance. The charge model generated by an embodiment can predict a charge at an input of a cell instance for an arbitrary input voltage waveform and can address (e.g., reduce or negate) a time delay impact the Miller effect has on the cell instance.