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1.发明公开公开(公告)号：US20230297386A1
公开(公告)日：2023-09-21
申请号：US18013807
申请日：2021-05-25
发明人： Jinhua TAO , Shaoli LIU
CPC分类号： G06F9/3867 , G06F9/30036 , G06F9/30025
摘要： A computing apparatus may be included in a combined processing apparatus. The combined processing apparatus may further include a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus may further include a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the apparatus and other processing apparatus. Efficiency of various operations in data processing fields including, for example, an artificial intelligence field can be improved so that overall overheads and costs of the operations can be reduced.
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2.发明公开公开(公告)号：US20230315477A1
公开(公告)日：2023-10-05
申请号：US18013748
申请日：2021-05-19
发明人： Xin YU , Shaoli LIU , Jinhua TAO
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3836
摘要： A computing apparatus may be included in a combined processing apparatus. The combined processing apparatus may further include a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus may further include a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus respectively. The storage apparatus is used to store data of the apparatus and other processing apparatus. Efficiency of various operations in data processing fields including, for example, an artificial intelligence field may be improved so that overall overheads and costs of the operations can be reduced.
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公开(公告)号：US20230259780A1
公开(公告)日：2023-08-17
申请号：US18003821
申请日：2021-10-14
发明人： Yufeng GAO , Shibing ZHU , Shaoli LIU , Xishan ZHANG , Deyuan HE
IPC分类号： G06N3/084
CPC分类号： G06N3/084
摘要： The present disclosure relates to a method and apparatus for sparsification training of a neural network model, a board card, and a readable storage medium. The data processing apparatus of the present disclosure is implemented as a computing apparatus and included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the computing apparatus and other processing apparatus. Embodiments of the present disclosure provide a solution related to the sparsification training of the neural network model, which improves operation ability of the neural network model and improves processing efficiency of a machine.
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公开(公告)号：US20230169144A1
公开(公告)日：2023-06-01
申请号：US17920372
申请日：2021-02-08
发明人： Shaoli LIU , Deyuan HE , Daofu LIU
CPC分类号： G06F17/16 , G06F7/50 , G06F7/523 , G06F7/5443
摘要： The present disclosure relates to an operation method, a processor, and related products that improve operation efficiency during matrix multiplication. The products include a storage component, an interface apparatus, a control component, and the an artificial intelligence chip. The artificial intelligence chip is connected to the storage component, the control component, and the interface apparatus, respectively. The storage component stores data. The interface apparatus implements data transfer between the artificial intelligence chip and an external device. The control component monitors a state of the artificial intelligence chip. .
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公开(公告)号：US20230024840A1
公开(公告)日：2023-01-26
申请号：US17929730
申请日：2022-09-05
发明人： Tianshi CHEN , Shaoli LIU , Zai WANG , Shuai HU
摘要： The present disclosure provides a computing method that is applied to a computing device. The computing device includes: a memory, a register unit, and a matrix computing unit. The method includes the following steps: controlling, by the computing device, the matrix computing unit to obtain a first operation instruction, where the first operation instruction includes a matrix reading instruction for a matrix required for executing the instruction; controlling, by the computing device, an operating unit to send a reading command to the memory according to the matrix reading instruction; and controlling, by the computing device, the operating unit to read a matrix corresponding to the matrix reading instruction in a batch reading manner, and executing the first operation instruction on the matrix. The technical solutions in the present disclosure have the advantages of fast computing speed and high efficiency.
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6.发明公开公开(公告)号：US20230297270A1
公开(公告)日：2023-09-21
申请号：US18013976
申请日：2021-08-03
发明人： Jinhua TAO , Shaoli LIU
CPC分类号： G06F3/0655 , G06F17/16 , G06F3/0604 , G06F3/0679
摘要： A data processing apparatus is included in a computing apparatus. The computing apparatus is included in a combined processing apparatus. The combined processing apparatus includes a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the computing apparatus and other processing apparatus. It can be widely used in various conversions of multi-dimension data and improve data conversion efficiency.
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7.发明公开公开(公告)号：US20230297387A1
公开(公告)日：2023-09-21
申请号：US18013589
申请日：2021-05-19
发明人： Xin YU , Shaoli LIU , Jinhua TAO
CPC分类号： G06F9/3871 , G06F9/3001
摘要： A calculation apparatus is included in a combined processing apparatus, which also includes a general interconnection interface and other processing apparatuses. The calculation apparatus interacts with other processing apparatuses to jointly complete calculations specified by users. The combined processing apparatus also includes a storage apparatus. The storage apparatus is respectively connected to a device and other processing apparatuses and is used for storing data of the device and data of other processing apparatuses. Operational efficiency of calculation of every kind of data processing fields including an artificial intelligence field can be improved, thereby decreasing overall overheads and cost of the calculation.
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公开(公告)号：US20230229393A1
公开(公告)日：2023-07-20
申请号：US18013398
申请日：2021-09-23
发明人： Enhe LIU , Qi LI , Boyu QIAN , Shaoli LIU , Jun LIANG
IPC分类号： G06F7/485
CPC分类号： G06F7/485
摘要： An accumulation apparatus according to an embodiment accumulates a plurality of floating point numbers in an identification cluster. A base exponent is identified, and, then, an accumulation cluster is filtered according to the base exponent, and floating point numbers in the accumulation cluster are accumulated. A small circuit area, low power consumption, and high precision can be achieved.
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公开(公告)号：US20230305840A1
公开(公告)日：2023-09-28
申请号：US18003687
申请日：2021-05-18
发明人： Jinhua TAO , Xin YU , Shaoli LIU
CPC分类号： G06F9/30014 , G06F7/544
摘要： The present disclosure discloses a computing apparatus, an integrated circuit chip, a board card, a device, and a method. The computing apparatus may be included in a combined processing apparatus. The combined processing apparatus may further include an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus may further include a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the computing apparatus and other processing apparatus. A solution of the present disclosure may use at least two pieces of small bit width data representing large bit width data to perform operation processing, so that processing capacity of a processor is not influenced by a bit width of the processor.
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