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1.发明公开公开(公告)号：US20230297270A1
公开(公告)日：2023-09-21
申请号：US18013976
申请日：2021-08-03
发明人： Jinhua TAO , Shaoli LIU
CPC分类号： G06F3/0655 , G06F17/16 , G06F3/0604 , G06F3/0679
摘要： A data processing apparatus is included in a computing apparatus. The computing apparatus is included in a combined processing apparatus. The combined processing apparatus includes a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the computing apparatus and other processing apparatus. It can be widely used in various conversions of multi-dimension data and improve data conversion efficiency.
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公开(公告)号：US20230185595A1
公开(公告)日：2023-06-15
申请号：US17923677
申请日：2021-05-07
发明人： Xiaofu Meng , Haibo Lu
CPC分类号： G06F9/45558 , G06F9/4856 , G06F2009/4557
摘要： A computation apparatus according to an embodiment is included in an integrated circuit apparatus, which includes a general interconnection interface and other processing apparatuses. The computation apparatus interacts with other processing apparatuses to jointly complete computation operations specified by users. The integrated circuit apparatus also includes a storage apparatus. The storage apparatus is respectively connected to the computation apparatus and the other processing apparatuses and is used for storing data of the computation apparatus and other processing apparatuses.
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公开(公告)号：US20230153157A1
公开(公告)日：2023-05-18
申请号：US17920940
申请日：2021-03-15
发明人： Lu CHAO , Fan LIANG , Qinglong CHAI , Xiao ZHANG , Yanqiang GAO , Yongzhe SUN , Zhiyong LI , Chen ZHANG , Tian MENG
CPC分类号： G06F9/5038 , G06F9/54 , G06F9/4881
摘要： A communication configuration apparatus for performing inter-node communication based on a plurality of processing nodes may be included in a combined processing apparatus. The combined processing apparatus further includes an interconnection interface and other processing apparatus. The communication configuration apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the communication configuration apparatus and other processing apparatuses, respectively. The storage apparatus is used for storing data of the communication configuration apparatus and other processing apparatus. A technical solution of the present disclosure may improve efficiency of the inter-chip communication.
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公开(公告)号：US11501158B2
公开(公告)日：2022-11-15
申请号：US16171284
申请日：2018-10-25
发明人： Daofu Liu , Xiao Zhang , Shaoli Liu , Tianshi Chen , Yunji Chen
摘要： Aspects for vector operations in neural network are described herein. The aspects may include a controller unit configured to receive an instruction to generate a random vector that includes one or more elements. The instruction may include a predetermined distribution, a count of the elements, and an address of the random vector. The aspects may further include a computation module configured to generate the one or more elements, wherein the one or more elements are subject to the predetermined distribution.
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公开(公告)号：US12067234B2
公开(公告)日：2024-08-20
申请号：US18003689
申请日：2021-06-24
发明人： Haibo Lu , Xiaofu Meng
CPC分类号： G06F3/0604 , G06F3/0647 , G06F3/0679 , G06F9/45558 , G06F2009/45579
摘要： The present disclosure relates to a device and a method for implementing live migration, where an on-chip system of the present disclosure is comprised in an integrated circuit apparatus, which comprises a general interconnection interface and other processing apparatuses. The computation apparatus interacts with other processing apparatuses to jointly complete computing operations specified by users. The integrated circuit apparatus also comprises a storage apparatus. The storage apparatus is respectively connected to the computation apparatus and other processing apparatuses and is used for storing data of the computation apparatus and other processing apparatuses.
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公开(公告)号：US20240070445A1
公开(公告)日：2024-02-29
申请号：US18257723
申请日：2021-09-23
发明人： Yufeng GAO , Shibing ZHU , Haoyuan HE
摘要： The present disclosure discloses a data processing circuit, a data processing method, and related products. The data processing circuit is implemented as a computing apparatus included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a user specified computation operation. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the computing apparatus and other processing apparatus. The solution disclosed in the present disclosure provides hardware implementation for operations related to structured sparsity, which can simplify processing and improve processing efficiency of a machine.
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7.发明公开公开(公告)号：US20230315477A1
公开(公告)日：2023-10-05
申请号：US18013748
申请日：2021-05-19
发明人： Xin YU , Shaoli LIU , Jinhua TAO
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3836
摘要： A computing apparatus may be included in a combined processing apparatus. The combined processing apparatus may further include a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus may further include a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus respectively. The storage apparatus is used to store data of the apparatus and other processing apparatus. Efficiency of various operations in data processing fields including, for example, an artificial intelligence field may be improved so that overall overheads and costs of the operations can be reduced.
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公开(公告)号：US20230259780A1
公开(公告)日：2023-08-17
申请号：US18003821
申请日：2021-10-14
发明人： Yufeng GAO , Shibing ZHU , Shaoli LIU , Xishan ZHANG , Deyuan HE
IPC分类号： G06N3/084
CPC分类号： G06N3/084
摘要： The present disclosure relates to a method and apparatus for sparsification training of a neural network model, a board card, and a readable storage medium. The data processing apparatus of the present disclosure is implemented as a computing apparatus and included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the computing apparatus and other processing apparatus. Embodiments of the present disclosure provide a solution related to the sparsification training of the neural network model, which improves operation ability of the neural network model and improves processing efficiency of a machine.
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公开(公告)号：US20230214322A1
公开(公告)日：2023-07-06
申请号：US17998892
申请日：2021-05-12
发明人： Xiaofu MENG , Tian ZHI , Zhenxing ZHANG , Xunyu CHEN
IPC分类号： G06F12/06 , G06N3/0464
CPC分类号： G06F12/06 , G06N3/0464
摘要： The present disclosure relates to a method, a device and a computation apparatus for allocating a space address to data in a memory, where the computation apparatus is included in a combined processing apparatus, which includes a general interconnection interface and other processing apparatuses. The computation apparatus interacts with other processing apparatuses to jointly complete computations specified by the user. The combined processing apparatus also includes a storage apparatus. The storage apparatus is respectively connected to the computation apparatus and the other processing apparatuses, and is used for storing data of the computation apparatus and other processing apparatuses. The technical solutions of the present disclosure improve utilization of storage space of the memory.
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公开(公告)号：US20230169144A1
公开(公告)日：2023-06-01
申请号：US17920372
申请日：2021-02-08
发明人： Shaoli LIU , Deyuan HE , Daofu LIU
CPC分类号： G06F17/16 , G06F7/50 , G06F7/523 , G06F7/5443
摘要： The present disclosure relates to an operation method, a processor, and related products that improve operation efficiency during matrix multiplication. The products include a storage component, an interface apparatus, a control component, and the an artificial intelligence chip. The artificial intelligence chip is connected to the storage component, the control component, and the interface apparatus, respectively. The storage component stores data. The interface apparatus implements data transfer between the artificial intelligence chip and an external device. The control component monitors a state of the artificial intelligence chip. .
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