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公开(公告)号：US6087853A
公开(公告)日：2000-07-11
申请号：US100939
申请日：1998-06-22
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K19/0005
摘要： CMOS technology is used to create a controlled output impedance output buffer circuit. An output buffer driver uses buffer circuits having impedance elements with linear characteristics. A control circuit uses a known impedance load to control the impedance of the buffer circuits. The control circuit monitors a known current flowing through the known impedance load to determine whether the output buffer circuit's output impedance needs to be adjusted to match a transmission line's impedance. Adjustments occur when the control circuit generates control signals to turn on or off various buffer circuits (and their impedance elements) contained within the output driver. In doing so, the output buffer circuit ensures that its output impedance will match the impedance of a transmission line over the entire range of output voltages regardless of the variations caused by the manufacturing process, operation temperature and power supply voltage.
摘要翻译： CMOS技术用于创建受控输出阻抗输出缓冲电路。 输出缓冲器驱动器使用具有线性特性的阻抗元件的缓冲电路。 控制电路使用已知的阻抗负载来控制缓冲电路的阻抗。 控制电路监测流过已知阻抗负载的已知电流，以确定输出缓冲电路的输出阻抗是否需要调整以匹配传输线的阻抗。 当控制电路产生控制信号以导通或关闭包含在输出驱动器内的各种缓冲电路（及其阻抗元件）时，发生调整。 在这样做时，输出缓冲电路确保其输出阻抗将与输出电压的整个范围内的传输线的阻抗匹配，而不管制造过程，操作温度和电源电压引起的变化如何。
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公开(公告)号：US07498860B2
公开(公告)日：2009-03-03
申请号：US11691590
申请日：2007-03-27
申请人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03L5/00
CPC分类号： H03K19/017581 , H03K19/01759
摘要： A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.
摘要翻译： 作为提供给缓冲电路的第一控制信号的函数，缓冲器电路有选择地以至少第一模式和第二模式中的至少一个工作。 缓冲电路包括接口电路，其操作以接收参考第一电压电平的至少第二和第三控制信号，并产生参考第二电压电平的输出信号，第二电压电平大于第一电压电平。 输出信号是第一模式中的第二控制信号的函数，并且是第二模式中的第三控制信号的函数。 缓冲电路还包括耦合到接口电路的至少第一和第二电路部分，第一和第二电路部分中的每一个包括至少一个控制输入，其操作以接收由接口电路产生的输出信号。
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公开(公告)号：US20080238399A1
公开(公告)日：2008-10-02
申请号：US11691590
申请日：2007-03-27
申请人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： G05F5/00
CPC分类号： H03K19/017581 , H03K19/01759
摘要： A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.
摘要翻译： 作为提供给缓冲电路的第一控制信号的函数，缓冲器电路有选择地以至少第一模式和第二模式中的至少一个工作。 缓冲电路包括接口电路，其操作以接收参考第一电压电平的至少第二和第三控制信号，并产生参考第二电压电平的输出信号，第二电压电平大于第一电压电平。 输出信号是第一模式中的第二控制信号的函数，并且是第二模式中的第三控制信号的函数。 缓冲电路还包括耦合到接口电路的至少第一和第二电路部分，第一和第二电路部分中的每一个包括至少一个控制输入，其操作以接收由接口电路产生的输出信号。
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公开(公告)号：US08373441B1
公开(公告)日：2013-02-12
申请号：US13236914
申请日：2011-09-20
申请人： John A. Milinichik , Peter J. Nicholas , Carol A. Huber , Antonio M. Marques , Daniel J. Delpero
发明人： John A. Milinichik , Peter J. Nicholas , Carol A. Huber , Antonio M. Marques , Daniel J. Delpero
CPC分类号： G06F17/5068
摘要： Described embodiments provide for a semiconductor device comprising a core and one or more input/output (I/O) buffers surrounding the core. The I/O buffers are adapted to transfer signals associated with core circuitry of the core. The I/O buffers comprise I/O cells having a first orientation and I/O cells having a second orientation. Each I/O cell has a corresponding translator having low voltage transistors in a corresponding footprint. The low voltage transistors in the first orientation I/O cells have the first orientation, and the low voltage transistors in the second orientation I/O cells have the first orientation. The footprints of the first orientation I/O cells and the second orientation I/O cells are compatible with one another.
摘要翻译： 所描述的实施例提供了一种半导体器件，其包括芯和围绕芯的一个或多个输入/输出（I / O）缓冲器。 I / O缓冲器适于传输与核心的核心电路相关联的信号。 I / O缓冲器包括具有第一取向的I / O单元和具有第二取向的I / O单元。 每个I / O单元具有相应的占空比中具有低电压晶体管的对应的转换器。 第一定向I / O单元中的低电压晶体管具有第一取向，并且第二取向I / O单元中的低电压晶体管具有第一取向。 第一定向I / O单元和第二定向I / O单元的脚印彼此兼容。
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