公开(公告)号：US6087853A

公开(公告)日：2000-07-11

申请号：US100939

申请日：1998-06-22

申请人： Carol A. Huber ,  Bernard L. Morris ,  Bijit T. Patel

发明人： Carol A. Huber ,  Bernard L. Morris ,  Bijit T. Patel

IPC分类号： H03K19/00 ,  H03K19/0175

CPC分类号： H03K19/0005

摘要： CMOS technology is used to create a controlled output impedance output buffer circuit. An output buffer driver uses buffer circuits having impedance elements with linear characteristics. A control circuit uses a known impedance load to control the impedance of the buffer circuits. The control circuit monitors a known current flowing through the known impedance load to determine whether the output buffer circuit's output impedance needs to be adjusted to match a transmission line's impedance. Adjustments occur when the control circuit generates control signals to turn on or off various buffer circuits (and their impedance elements) contained within the output driver. In doing so, the output buffer circuit ensures that its output impedance will match the impedance of a transmission line over the entire range of output voltages regardless of the variations caused by the manufacturing process, operation temperature and power supply voltage.

摘要翻译： CMOS技术用于创建受控输出阻抗输出缓冲电路。 输出缓冲器驱动器使用具有线性特性的阻抗元件的缓冲电路。 控制电路使用已知的阻抗负载来控制缓冲电路的阻抗。 控制电路监测流过已知阻抗负载的已知电流，以确定输出缓冲电路的输出阻抗是否需要调整以匹配传输线的阻抗。 当控制电路产生控制信号以导通或关闭包含在输出驱动器内的各种缓冲电路（及其阻抗元件）时，发生调整。 在这样做时，输出缓冲电路确保其输出阻抗将与输出电压的整个范围内的传输线的阻抗匹配，而不管制造过程，操作温度和电源电压引起的变化如何。

公开(公告)号：US5933027A

公开(公告)日：1999-08-03

申请号：US879212

申请日：1997-06-19

申请人： Bernard L. Morris ,  Bijit T. Patel

发明人： Bernard L. Morris ,  Bijit T. Patel

IPC分类号： H01L27/04 ,  H01L21/822 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/00315

摘要： An integrated circuit is implemented in a low-voltage technology and has an output driver. The output driver has circuitry adapted to generate an output voltage at an output node (e.g., PAD in FIG. 1) based on an input voltage (e.g., A). Within the output driver, a transistor is configured to limit the drain-to-source voltage drop across another transistor to enable the integrated circuit to tolerate, at its output node, voltages of magnitude up to two times the operating voltage of the integrated circuit. The invention enables low-voltage integrated circuits to be interfaced with other circuitry implemented in a relatively high-voltage technology, without suffering the adverse effects that can otherwise result in the low-voltage circuitry from such interfacing.

摘要翻译： 集成电路采用低压技术实现，并具有输出驱动器。 输出驱动器具有适于基于输入电压（例如，A）在输出节点（例如，图1中的PAD）产生输出电压的电路。 在输出驱动器内，晶体管被配置为限制跨另一晶体管的漏极 - 源极电压降，以使得集成电路在其输出节点容忍高达集成电路的工作电压的两倍的电压。 本发明使得低电压集成电路能够与在相对高压技术中实现的其它电路接口，而不会产生不利影响，否则可能导致低压电路不受这种接口的影响。

公开(公告)号：US20080238399A1

公开(公告)日：2008-10-02

申请号：US11691590

申请日：2007-03-27

申请人： Dipankar Bhattacharya ,  Carol A. Huber ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Carol A. Huber ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： G05F5/00

CPC分类号： H03K19/017581 ,  H03K19/01759

摘要： A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.

摘要翻译： 作为提供给缓冲电路的第一控制信号的函数，缓冲器电路有选择地以至少第一模式和第二模式中的至少一个工作。 缓冲电路包括接口电路，其操作以接收参考第一电压电平的至少第二和第三控制信号，并产生参考第二电压电平的输出信号，第二电压电平大于第一电压电平。 输出信号是第一模式中的第二控制信号的函数，并且是第二模式中的第三控制信号的函数。 缓冲电路还包括耦合到接口电路的至少第一和第二电路部分，第一和第二电路部分中的每一个包括至少一个控制输入，其操作以接收由接口电路产生的输出信号。

公开(公告)号：US07498860B2

公开(公告)日：2009-03-03

申请号：US11691590

申请日：2007-03-27

申请人： Dipankar Bhattacharya ,  Carol A. Huber ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Carol A. Huber ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03L5/00

CPC分类号： H03K19/017581 ,  H03K19/01759

摘要： A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.

摘要翻译： 作为提供给缓冲电路的第一控制信号的函数，缓冲器电路有选择地以至少第一模式和第二模式中的至少一个工作。 缓冲电路包括接口电路，其操作以接收参考第一电压电平的至少第二和第三控制信号，并产生参考第二电压电平的输出信号，第二电压电平大于第一电压电平。 输出信号是第一模式中的第二控制信号的函数，并且是第二模式中的第三控制信号的函数。 缓冲电路还包括耦合到接口电路的至少第一和第二电路部分，第一和第二电路部分中的每一个包括至少一个控制输入，其操作以接收由接口电路产生的输出信号。

公开(公告)号：US07642807B2

公开(公告)日：2010-01-05

申请号：US11768496

申请日：2007-06-26

申请人： Dipankar Bhattacharya ,  Gregg R. Harleman ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

发明人： Dipankar Bhattacharya ,  Gregg R. Harleman ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris

IPC分类号： H03K17/16

CPC分类号： H03K19/00376

摘要： A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.

摘要翻译： 以至少第一模式和第二模式之一工作的补偿缓冲器电路包括多个输出块和多个预驱动器，每个预驱动器具有连接到相应一个输出块的输入的输出。 输出块的各输出端连接在一起形成缓冲电路的输出。 输出块按顺序排列并且被二进制加权，使得给定的一个输出块的驱动强度大约是在给定输出块之前的输出块的驱动强度的两倍。 每个预驱动器根据提供给预驱动器的控制信号选择性地使连接到其上的相应输出块能够补偿用于缓冲电路可能经受的PVT变化的缓冲电路。 提供给预驱动器的各个控制信号共同表示二进制码字，第二模式中的二进制码字等效于第一模式中的二进制码字的算术移位。

公开(公告)号：US20080074171A1

公开(公告)日：2008-03-27

申请号：US11535198

申请日：2006-09-26

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

IPC分类号： G05F1/10

CPC分类号： H03K19/0016 ,  H01L27/0251 ,  H03K19/00315

摘要： An IC having improved reliability includes at least first and second circuit blocks and at least first and second power domains, the first circuit block being connected to the first power domain and the second circuit block being connected to the second power domain. The IC further includes at least one control circuit configured to generate at least first and second control signals. The first control signal is operative to selectively connect the first power domain to a first voltage supply, and the second control signal is operative to selectively connect the second power domain to a second voltage supply. The IC includes at least first and second clamp circuits, the first clamp circuit being connected to the first power domain, the second clamp circuit being connected to the second power domain. Each of the clamp circuits is operative to prevent a voltage on a corresponding power domain from rising above a prescribed voltage level for the corresponding power domain.

摘要翻译： 具有改进的可靠性的IC至少包括第一和第二电路块以及至少第一和第二电力域，第一电路块连接到第一电力域，第二电路块连接到第二电力域。 IC还包括被配置为产生至少第一和第二控制信号的至少一个控制电路。 第一控制信号用于选择性地将第一功率域连接到第一电压源，并且第二控制信号用于选择性地将第二功率域连接到第二电压源。 IC包括至少第一和第二钳位电路，第一钳位电路连接到第一电源域，第二钳位电路连接到第二电源域。 每个钳位电路可操作以防止相应功率域上的电压升高到对应功率域的规定电压电平以上。

公开(公告)号：US07276957B2

公开(公告)日：2007-10-02

申请号：US11239840

申请日：2005-09-30

申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Duane J. Loeper ,  Bernard L. Morris ,  Yehuda Smooha

发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Duane J. Loeper ,  Bernard L. Morris ,  Yehuda Smooha

IPC分类号： H03K

CPC分类号： H03K19/00315 ,  H03K2217/0018

摘要： A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.

摘要翻译： 用于限定其中形成有至少一个金属氧化物半导体器件的浮动阱的电压电位的电路包括感测电路，其可操作以检测浮动阱连接到的节点处的电压，并产生指示性的控制信号 节点处的电压是否基本上在电压范围内。 电压范围的较低值基本上等于低于电路的第一电源电压的阈值电压。 电压范围的较高值基本上等于高于第一电源电压的阈值电压。 用于定义浮动阱的电压电位的电路还包括电压发生器电路，其操作以接收控制信号并产生用于响应于控制信号设置阱的电压电位的偏置信号，偏置信号被控制在整个 电压范围。

公开(公告)号：US07170324B2

公开(公告)日：2007-01-30

申请号：US10891048

申请日：2004-07-15

申请人： Carol Ann Huber ,  John C. Kriz ,  Brian C. Lacey ,  Bernard L. Morris

发明人： Carol Ann Huber ,  John C. Kriz ,  Brian C. Lacey ,  Bernard L. Morris

IPC分类号： H03K5/12

CPC分类号： H03K17/163

摘要： A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.

摘要翻译： 用于具有可调节转换速率控制的集成电路的缓冲器设计，但与具有压摆率控制的常规缓冲器相比，制造空间要小得多。 将新的压摆率控制电路设计添加到互补金属氧化物半导体CMOS缓冲器中以在缓冲器中实现转换速率控制（例如，在高转换速率和低压摆率之间进行选择）。 新的压摆率控制电路需要明显较少的制造空间，并且当应用于给定集成电路中的每个缓冲器时，例如可以沿着集成电路的外围放置的输入/输出缓冲器，节省的成本是非同寻常的。

公开(公告)号：US06590433B2

公开(公告)日：2003-07-08

申请号：US09733445

申请日：2000-12-08

申请人： James T. Clee ,  Bernard L. Morris ,  James E. Guziak

发明人： James T. Clee ,  Bernard L. Morris ,  James E. Guziak

IPC分类号： H03B100

CPC分类号： H03K19/1736 ,  H03K19/018592

摘要： A bi-directional buffer includes the capability to turn the current mirror off when the bi-directional buffer is in the receive mode and quickly turn the current mirror on when the bi-directional buffer goes into the transmit mode. This is accomplished in part by a pair of switches included in the current mirror, which are controlled by enable signals. The switches are configured such that the output transistor of the current mirror is turned on when the bi-directional buffer is in the transmit mode, and turned off when the bi-directional buffer is in the receive mode. Further, a pull up circuit may be added to the current mirror to more quickly bring the gate of the output transistor of the current mirror to its conduction threshold voltage.

摘要翻译： 双向缓冲器包括当双向缓冲器处于接收模式时关闭当前镜像的能力，并且当双向缓冲器进入发送模式时，快速打开电流镜。 这部分由包括在电流镜中的一对开关实现，其由使能信号控制。 开关被配置为使得当双向缓冲器处于发送模式时电流镜的输出晶体管导通，并且当双向缓冲器处于接收模式时，该开关被断开。 此外，可以向电流镜添加上拉电路，以更快速地将电流镜的输出晶体管的栅极导通到其导通阈值电压。

公开(公告)号：US4278705A

公开(公告)日：1981-07-14

申请号：US92523

申请日：1979-11-08

申请人： Jorge Agraz-Guerena ,  Lewis E. Katz ,  Bernard L. Morris

发明人： Jorge Agraz-Guerena ,  Lewis E. Katz ,  Bernard L. Morris

IPC分类号： H01L21/324 ,  H01L21/762 ,  H01L21/316

CPC分类号： H01L21/3247 ,  H01L21/324 ,  H01L21/7621

摘要： A process for making dielectrically isolated silicon integrated circuits which use silicon oxide filled trenches to provide isolation is described. To minimize damage to the silicon, the trenches are filled by sequentially annealed oxidation process which involves alternately growing some oxide and then annealing to relieve stresses before growing more oxide.

摘要翻译： 描述了使用氧化硅填充的沟槽来提供隔离的用于制造介电隔离的硅集成电路的方法。 为了最小化对硅的损害，通过依次退火的氧化工艺填充沟槽，这涉及交替生长一些氧化物，然后退火以在生长更多氧化物之前减轻应力。