公开(公告)号：US11640196B2

公开(公告)日：2023-05-02

申请号：US17461923

申请日：2021-08-30

Applicant: Ceremorphic, Inc.

Inventor： Subba Reddy Kallam ,  Venkat Mattela ,  Aravinth Kumar Ayyappannair Radhadevi ,  Sesha Sairam Regulagadda

IPC: G06F1/06 ,  G06F1/3234 ,  G06F15/80 ,  H03M1/80 ,  H03M1/12 ,  G06F7/544 ,  H03M1/66

Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

公开(公告)号：US11893078B2

公开(公告)日：2024-02-06

申请号：US17006815

申请日：2020-08-29

Applicant: Ceremorphic, Inc.

Inventor： Aravinth Kumar Ayyappannair Radhadevi ,  Sesha Sairam Regulagadda

IPC: G06F17/16 ,  G06F7/544 ,  G06G7/16

CPC classification number: G06F17/16 ,  G06F7/5443 ,  G06G7/16

Abstract: A dot product multiplier for matrix operations for an A matrix of order 1×m with a coefficient B matrix of order m×m. Processing Elements (PEs) are arranged in an m×m array, the columns of the array summed to provide a dot product result. Each of the PEs contains a sign determiner and a plurality of analog multiplier cells, one multiplier cell for each value bit. The multipliers operate over four clock cycles, initializing a capacitor charge according to sign on a first clock phase, sharing charge on a second phase, canceling charge on a third phase, and outputting the resultant charge on a fourth phase, the resultant charge on each column representing the dot product for that column.