公开(公告)号：US11893249B2

公开(公告)日：2024-02-06

申请号：US17691046

申请日：2022-03-09

Applicant: Ceremorphic, Inc.

Inventor： Subba Reddy Kallam ,  Partha Sarathy Murali ,  Venkata Siva Prasad Pulagam ,  Anusha Biyyani ,  Venkatesh Vinjamuri ,  Shahabuddin Mohammed ,  Rahul Kumar Gurram ,  Akhil Soni

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/0625 ,  G06F3/068 ,  G06F3/0631 ,  G06F12/0646 ,  G06F2212/1028

Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.

公开(公告)号：US11640196B2

公开(公告)日：2023-05-02

申请号：US17461923

申请日：2021-08-30

Applicant: Ceremorphic, Inc.

Inventor： Subba Reddy Kallam ,  Venkat Mattela ,  Aravinth Kumar Ayyappannair Radhadevi ,  Sesha Sairam Regulagadda

IPC: G06F1/06 ,  G06F1/3234 ,  G06F15/80 ,  H03M1/80 ,  H03M1/12 ,  G06F7/544 ,  H03M1/66

Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

公开(公告)号：US11775306B2

公开(公告)日：2023-10-03

申请号：US17677198

申请日：2022-02-22

Applicant: Ceremorphic, Inc.

Inventor： Subba Reddy Kallam ,  Partha Sarathy Murali ,  Venkat Mattela ,  Venkata Siva Prasad Pulagam

IPC: G06F9/38 ,  G06F9/52 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/52

Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.