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公开(公告)号：US12242849B1
公开(公告)日：2025-03-04
申请号：US18238479
申请日：2023-08-26
Applicant: Ceremorphic, Inc.
Inventor： Heonchul Park , Venkat Mattela
Abstract: A computing system includes (1) a primary processor executing executable instructions and generating first instruction data associated with the executable instructions, (2) a secondary processor executing the executable instructions one or more clock cycles behind the primary processor and generating secondary instruction data associated with the executable instructions, (3) a first first-in first-out (FIFO) buffer for the primary processor, (4) a second FIFO buffer for the secondary processor, (5) circuitry storing at least some of the first instruction data in the first FIFO buffer and at least some of the second instruction data in the second FIFO buffer, (6) compare circuitry comparing a first portion of first instruction data and a second portion of second instruction data that are associated with a given clock cycle, and (7) control circuitry halting the primary and secondary processors responsive to a mismatch between the first portion and the second portion.
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公开(公告)号：US11640196B2
公开(公告)日：2023-05-02
申请号：US17461923
申请日：2021-08-30
Applicant: Ceremorphic, Inc.
Inventor： Subba Reddy Kallam , Venkat Mattela , Aravinth Kumar Ayyappannair Radhadevi , Sesha Sairam Regulagadda
Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).
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公开(公告)号：US11962298B1
公开(公告)日：2024-04-16
申请号：US17829091
申请日：2022-05-31
Applicant: Ceremorphic, Inc.
Inventor： Sanghamitra Debroy , Akshaykumar Salimath , Venkat Mattela
CPC classification number: H03K19/18 , H01F10/324 , H03K19/173 , H10N35/00 , H10N50/20 , H10N50/85
Abstract: A system and method for a logic device is disclosed. A first substrate, and a second substrate is provided, which are spaced apart from each other and manifests Spin orbit torque effect. A nanomagnet is disposed over the first substrate and the second substrate. A first charge current is passed through the first substrate and a second charge current is passed through the second substrate. A direction of flow of the first charge current and the second charge current defines an input value of either a first value or a second value. A spin in the nanomagnet is selectively oriented based on the direction of flow of the first charge current and the second charge current. The spin in the nanomagnet is selectively read to determine an output value as the first value or the second value. The logic device is configured as a XOR logic.
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公开(公告)号：US11917924B2
公开(公告)日：2024-02-27
申请号：US17234792
申请日：2021-04-19
Applicant: Ceremorphic, Inc.
Inventor： Venkat Mattela , Sanghamitra Debroy , Santhosh Sivasubramani
CPC classification number: H10N50/85 , G06F7/523 , H10N50/80 , H01F10/3286 , H03K19/20
Abstract: A multiplier device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A plurality of regions on a top surface are activated with a magnetic field in a first direction for a 1 value and in an opposite direction for a 0 value, the multiplication result presented as magnetic field direction on a plurality of output ferromagnetic regions.
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公开(公告)号：US12212316B1
公开(公告)日：2025-01-28
申请号：US17878025
申请日：2022-07-31
Applicant: Ceremorphic, Inc.
Inventor： Akshaykumar Salimath , Sanghamitra Debroy , Venkat Mattela
Abstract: A system and method for a logic device is disclosed. A plurality of synthetic antoferromagnet (SAF) nanotracks including a first input nanotrack, a second input nanotrack and an output nanotrack are disposed over a substrate along a first axis. Output nanotrack is disposed between the input nanotracks. Each nanotrack have a first end and a second end. A SAF connector nanotrack connects the first input nanotrack, the second input nanotrack, and the output nanotrack. An input value is defined at a first end of the input nanotracks by selectively nucleating a SAF skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. A charge current is passed along the first axis to move nucleated skyrmion to the second end of the output nanotrack. Skyrmion at the output indicates an output value of the first value.
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Patent Agency Ranking
公开(公告)号：US12211536B1
公开(公告)日：2025-01-28
申请号：US17878022
申请日：2022-07-31
Applicant: Ceremorphic, Inc.
Inventor： Sanghamitra Debroy , Akshaykumar Salimath , Venkat Mattela
Abstract: A system and method for a logic device is disclosed. A plurality of substrates are provided. At least one input nanomagnet is disposed over each of the plurality of substrates. The plurality of input nanomagnets are disposed substantially equidistant from each other. The plurality of input nanomagnets are each a single domain nanomagnet. A spacer layer is disposed over the plurality of input nanomagnets. An output magnet is disposed over the spacer layer.
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公开(公告)号：US12143313B1
公开(公告)日：2024-11-12
申请号：US17671569
申请日：2022-02-14
Applicant: Ceremorphic, Inc.
Inventor： Suyash Kandele , Sumant Kumar Singh , Joydeep Kumar Devnath , Venkat Mattela , Govardhan Mattela , Heonchul Park
IPC: H04L49/1546 , H04L49/00
Abstract: A system and method for a switching network is disclosed. A plurality of first switching assemblies, second switching assemblies and intermediate switching assemblies with each of the first switching assemblies, second switching assemblies and intermediate switching assemblies having at least two input ports and output ports is provided. Selective one of the two input ports is configured to receive a data to be processed and delivered at a designated one of the output ports. Received data passes through one or more selective first switching assemblies, one or more intermediate switching assemblies and one or more selective second switching assemblies, before the received data is delivered to the designated port. A plurality of additional data is received in one or more of the input ports to be delivered to one or more designated output ports is processed before the received data is delivered to the designated one of the output ports.
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公开(公告)号：US12211641B1
公开(公告)日：2025-01-28
申请号：US17734061
申请日：2022-04-30
Applicant: Ceremorphic, Inc.
Inventor： Sanghamitra Debroy , Akshaykumar Salimath , Venkat Mattela
Abstract: A system and method for a logic device is disclosed. A first input nanotrack, a second input nanotrack and an output nanotrack are disposed over a substrate along a first axis. Output nanotrack is disposed between the input nanotracks. Each nanotrack have a first end and a second end. A connector nanotrack connects the first input nanotrack, the second input nanotrack, and the output nanotrack. An input value is defined at a first end of the input nanotracks by selectively nucleating a skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. Nucleated skyrmion moves to the second end of the output nanotrack when a charge current is passed along the first axis. Presence of the skyrmion at the second end indicates an output value of the first value.
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公开(公告)号：US12111913B2
公开(公告)日：2024-10-08
申请号：US17485436
申请日：2021-09-26
Applicant: Ceremorphic, Inc.
Inventor： Lizy Kurian John , Heonchul Park , Venkat Mattela
CPC classification number: G06F21/52 , G06F9/3001 , G06F9/30076 , G06F2221/033
Abstract: A secure processor with fault detection has a core thread which executes with a redundant branch processor thread. In one configuration, the core thread is operative on a fully functional core processor configured to execute a complete instruction set, and the redundant branch processor thread contains only initialization instructions and flow control instructions such as branch instructions and is operative on a redundant branch processor which is configured to execute a subset of the complete instruction set, specifically a branch control variable initialization and a branch instruction, thereby greatly simplifying the redundant branch processor architecture. Fault conditions are detected by comparing either a history of branch taken/not taken and branch targets, or a comparison of program counter activity for the core thread and redundant branch processor thread.
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公开(公告)号：US12081213B1
公开(公告)日：2024-09-03
申请号：US17829127
申请日：2022-05-31
Applicant: Ceremorphic, Inc.
Inventor： Akshaykumar Salimath , Sanghamitra Debroy , Venkat Mattela
CPC classification number: H03K19/0008 , H03K19/08
Abstract: A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. Nanotrack along the second axis extend beyond the central portion to define an output portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis and the second axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the output portion and indicates a first value when skyrmion is present.
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