公开(公告)号：US5467306A

公开(公告)日：1995-11-14

申请号：US85427

申请日：1993-10-04

申请人： Cetin Kaya ,  Wayland B. Holland ,  Rabah Mezenner

发明人： Cetin Kaya ,  Wayland B. Holland ,  Rabah Mezenner

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/12 ,  G11C16/00

CPC分类号： G11C16/12

摘要： The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11 ) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.

摘要翻译： 本发明的方法允许在编程期间使用较小的字线电压Vp1。 此外，当用于闪存编程存储器单元阵列（10）时，该方法导致阈值电压Vt的相对较窄的分布。 本发明的方法通过反向偏置正被编程的单元的源极（11）/衬底（23）结，增加了压电栅极电流效率。 反向偏置是通过例如通过向源极（11）施加偏置电压或者通过放置与源极（11）串联的二极管（27），电阻器（29）或其它阻抗来实现的。 反向偏置在闪存编程压缩期间限制正在编程的单元的源电流（Is）和整个阵列的源电流（Is）。

公开(公告)号：US5428578A

公开(公告)日：1995-06-27

申请号：US106095

申请日：1993-08-12

申请人： Cetin Kaya ,  Wayland B. Holland ,  Rabah Mezenner

发明人： Cetin Kaya ,  Wayland B. Holland ,  Rabah Mezenner

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16

CPC分类号： G11C16/16

摘要： The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11 ) and a drain (12). The method comprises connecting the control gates (14) to a control-gate voltage (Vg), connecting the sources (11 ) to a source voltage (Vs) having a higher potential than the, control-gate voltage (Vg) and connecting the drains (12) to a drain subcircuit (DS) having, in at least one embodiment, a potential (Vd) between the control-gate voltage (Vg) and the source voltage (Vs), the drain subcircuit (DS) having a sufficiently low impedance to allow current flow between the sources (11) and drains (12) at a time during the erasing operation. The drain subcircuit (DS) allows for optimum threshold voltage distribution and a part of the drain potential (Vd) may be fed back to arrest the erase process at an optimum point.

摘要翻译： 本发明的擦除方法导致当用于闪存一组浮栅型存储单元（10）时阈值电压的相对较窄的分布。 每个单元包括控制栅极（14），源极（11）和漏极（12）。 该方法包括将控制栅极（14）连接到控制栅极电压（Vg），将源极（11）连接到具有比控制栅极电压（Vg）更高的电位的源极电压（Vs），并将 在至少一个实施例中，在控制栅极电压（Vg）和源极电压（Vs）之间具有电位（Vd）的漏极分支电路（DS）的漏极（12），漏极子电路（DS） 低阻抗，以允许在擦除操作期间的电源（11）和漏极（12）之间的电流流动。 漏极分支电路（DS）允许最佳的阈值电压分布，并且可以反馈一部分漏极电位（Vd）以在最佳点停止擦除过程。

公开(公告)号：US5596528A

公开(公告)日：1997-01-21

申请号：US532313

申请日：1995-09-22

申请人： Cetin Kaya ,  Wayland B. Holland ,  Rabah Mezenner

发明人： Cetin Kaya ,  Wayland B. Holland ,  Rabah Mezenner

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/12 ,  G11C16/00

CPC分类号： G11C16/12

摘要： The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.

摘要翻译： 本发明的方法允许在编程期间使用较小的字线电压Vp1。 此外，当用于闪存编程存储器单元阵列（10）时，该方法导致阈值电压Vt的相对较窄的分布。 本发明的方法通过反向偏置正被编程的单元的源极（11）/衬底（23）结，增加了压电栅极电流效率。 反向偏置是通过例如通过向源极（11）施加偏置电压或者通过放置与源极（11）串联的二极管（27），电阻器（29）或其它阻抗来实现的。 反向偏置在闪存编程压缩期间限制正在编程的单元的源电流（Is）和整个阵列的源电流（Is）。

公开(公告)号：US5526315A

公开(公告)日：1996-06-11

申请号：US387983

申请日：1995-02-13

申请人： Cetin Kaya ,  Wayland B. Holland ,  Rabah Mezenner

发明人： Cetin Kaya ,  Wayland B. Holland ,  Rabah Mezenner

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16

CPC分类号： G11C16/16

摘要： The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11) and a drain (12). The method comprises connecting the control gates (14) to a control-gate voltage (Vg), connecting the sources (11) to a source voltage (Vs) having a higher potential than the control-gate voltage (Vg) and connecting the drains (12) to a drain subcircuit (DS) having, in at least one embodiment, a potential (Vd) between the control-gate voltage (Vg) and the source voltage (Vs), the drain subcircuit (DS) having a sufficiently low impedance to allow current flow between the sources (11) and drains (12) at a time during the erasing operation. The drain subcircuit (DS) allows for optimum threshold voltage distribution and a part of the drain potential (Vd) may be fed back to arrest the erase process at an optimum point.

摘要翻译： 本发明的擦除方法导致当用于闪存一组浮栅型存储单元（10）时阈值电压的相对较窄的分布。 每个单元包括控制栅极（14），源极（11）和漏极（12）。 该方法包括将控制栅极（14）连接到控制栅极电压（Vg），将源极（11）连接到具有比控制栅极电压（Vg）更高的电位的源极电压（Vs），并将漏极 （12）至漏极分支电路（DS），在至少一个实施例中，具有控制栅极电压（Vg）和源极电压（Vs）之间的电位（Vd），漏极子电路（DS）具有足够低的电位 阻抗，以在擦除操作期间的一个时间允许电流（11）和漏极（12）之间的电流流动。 漏极分支电路（DS）允许最佳的阈值电压分布，并且可以反馈一部分漏极电位（Vd）以在最佳点停止擦除过程。

公开(公告)号：US07317355B2

公开(公告)日：2008-01-08

申请号：US11125968

申请日：2005-05-10

申请人： Shifeng Zhao ,  Cetin Kaya ,  James Teng ,  Claus Neesgaard ,  Lieyi Fang ,  Jeff Berwick

发明人： Shifeng Zhao ,  Cetin Kaya ,  James Teng ,  Claus Neesgaard ,  Lieyi Fang ,  Jeff Berwick

IPC分类号： H03F3/217

CPC分类号： H03K17/0822 ,  H03K17/162

摘要： A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection circuit for detecting an over-current condition in a power FET comprises a current generator circuit operative to generate a reference current and a plurality of matched FETs operative to receive the reference current and provide a reference voltage, the matched FETs being matched to each other and to the power FET. The over-current detection circuit also comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded the reference voltage.

摘要翻译： 提供了用于检测功率场效应晶体管（FET）中的过电流状态的系统和方法。 在一个实施例中，用于检测功率FET中的过电流状态的过电流检测电路包括用于产生参考电流的电流发生器电路和用于接收参考电流并提供参考电压的多个匹配FET， 匹配的FET彼此匹配并连接到功率FET。 过电流检测电路还包括比较器，用于测量功率FET的漏极 - 源极电压，并提供指示功率FET的漏极 - 源极电压已经超过参考电压的输出。

公开(公告)号：US06797935B2

公开(公告)日：2004-09-28

申请号：US10251732

申请日：2002-09-20

申请人： Cetin Kaya ,  Julian Chen

发明人： Cetin Kaya ,  Julian Chen

IPC分类号： H01L3100

CPC分类号： H04N5/3745 ,  H01L27/14609

摘要： A forward biased diode 40 is used to charge up a photodiode 26 rather than an NMOS transistor. This photodiode charging mechanism increases the dynamic range and optical response of active pixel arrays, and improves the scalability of the pixel element.

摘要翻译： 正向偏置二极管40用于对光电二极管26充电，而不是NMOS晶体管。 该光电二极管充电机构增加了有源像素阵列的动态范围和光学响应，并提高了像素元件的可扩展性。

公开(公告)号：US06306690B1

公开(公告)日：2001-10-23

申请号：US09389144

申请日：1999-09-02

申请人： Cetin Kaya ,  Stanton P. Ashburn

发明人： Cetin Kaya ,  Stanton P. Ashburn

IPC分类号： H01L21332

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： The invention comprises an integrated circuit including integral high and low-voltage peripheral transistors and a method for making the integrated circuit. In one aspect of the invention, a method of integrating high and low voltage transistors into a floating gate memory array comprises the steps of forming a tunnel oxide layer outwardly from a semiconductor substrate, forming a floating gate layer disposed outwardly from the tunnel oxide layer and forming an insulator layer disposed outwardly from the floating gate layer to create a first intermediate structure. The method further includes the steps of masking a first region and a second region of the first intermediate structure leaving a third region unmasked, removing at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer from the third region and forming a first dielectric layer disposed outwardly from the substrate in a region approximately coextensive with the third region. The second region and the third region are masked, leaving the first region unmasked. Then, at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer is removed from the first region. A second dielectric layer is formed outwardly from the substrate and the first dielectric layer in a region approximately coextensive with the first region and the third regions, respectively.

摘要翻译： 本发明包括集成电路，包括集成的高电压和低电压外围晶体管以及用于制造集成电路的方法。 在本发明的一个方面，一种将高压和低压晶体管集成到浮动栅极存储器阵列中的方法包括以下步骤：从半导体衬底向外形成隧道氧化层，形成从隧道氧化物层向外设置的浮动栅层;以及 形成从所述浮栅层向外设置以形成第一中间结构的绝缘体层。 该方法还包括以下步骤：掩蔽第一中间结构的第一区域和第二区域，留下未被掩蔽的第三区域，从第三区域去除绝缘体层，浮动栅极层和隧道氧化物层的至少一部分，以及 形成在与所述第三区域大致共同延伸的区域中从所述基板向外设置的第一介电层。 第二个区域和第三个区域被掩盖，使第一个区域被隐藏。 然后，从第一区域去除绝缘体层，浮栅和隧道氧化物层的至少一部分。 在与第一区域和第三区域大致共同延伸的区域中，从基板和第一介电层向外形成第二电介质层。

公开(公告)号：US6072212A

公开(公告)日：2000-06-06

申请号：US978361

申请日：1997-11-25

申请人： Cetin Kaya ,  Kemal Tamer San

发明人： Cetin Kaya ,  Kemal Tamer San

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L33/00

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： This invention provides a cost-effective, easy-to-integrate Flash EPROM cell array. Starting with a substrate (31) of first conductivity-type, a first diffusion (30) of second conductivity-type forms the sources (11), and the connections between sources, of all of the memory cells (10) of the array. A second diffusion (32) of first conductivity-type forms the channel of at least one memory cell (10) in the array. A floating gate (13) and a control gate (14) of that memory cell (10) are located over, and insulated from, a junction of the first diffusion and the second diffusion. A third diffusion (33) of second conductivity-type is isolated in the second diffusion (32) to form the drain (12) of the memory cell (10). During operation, only positive voltages may be used for programming and erasing of the cells (10), thus eliminating the need for negative voltages and for triple-well diffusions. The cell array of this invention requires little or no current for Fowler-Nordheim erase operation. Therefore, there is no need for wordline (15) decoding of large arrays. In addition to the above features, use of the cell array of this invention saves space by eliminating, in certain types of prior-art arrays, the need for space-consuming columnar metal source lines. In that same type of array, a self-aligned-source etch step and a self-aligned-source implant step are eliminated.

摘要翻译： 本发明提供了一种成本有效的易于集成的闪存EPROM单元阵列。 从第一导电类型的衬底（31）开始，第二导电类型的第一扩散（30）形成源极（11）以及阵列的所有存储器单元（10）的源极之间的连接。 第一导电型的第二扩散（32）形成阵列中的至少一个存储单元（10）的沟道。 该存储单元（10）的浮动栅极（13）和控制栅极（14）位于第一扩散部分和第二扩散部分之间并与其绝缘。 在第二扩散（32）中隔离第二导电类型的第三扩散（33）以形成存储单元（10）的漏极（12）。 在操作期间，只有正电压可用于对电池（10）进行编程和擦除，从而消除对负电压和三阱扩散的需要。 本发明的电池阵列对于Fowler-Nordheim擦除操作需要很少的或没有电流。 因此，不需要对大阵列进行字线（15）解码。 除了上述特征之外，本发明的电池阵列的使用通过在某些类型的现有技术的阵列中消除对空间消耗的柱状金属源极线的需求来节省空间。 在相同类型的阵列中，消除了自对准源蚀刻步骤和自对准源注入步骤。

公开(公告)号：US5482880A

公开(公告)日：1996-01-09

申请号：US66816

申请日：1993-05-24

申请人： Cetin Kaya ,  David Liu

发明人： Cetin Kaya ,  David Liu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11517 ,  H01L27/115 ,  H01L29/7886

摘要： In one embodiment, a non-volatile memory cell structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region 21. A floating gate 13 is formed over and insulated from the channel region 21 and a control gate 14 is formed over and insulated from the floating gate 13. A lightly doped region 20 is formed in the channel 21 beneath the floating gate 13 and adjoining the source region 11. The lightly doped region 20 is spaced from the surface of said substrate 8. Other embodiments and processes are also disclosed.

摘要翻译： 在一个实施例中，非易失性存储单元结构10包括形成在半导体衬底8的表面中并被沟道区21分隔的重掺杂源极11和漏极12区域。浮置栅极13形成在沟道上并与沟道绝缘 区域21和控制栅极14形成在浮置栅极13之上并与浮动栅极13绝缘。轻掺杂区域20形成在浮置栅极13下方的沟道21中并与源极区域11相邻。轻掺杂区域20与 还公开了其它实施方案和方法。

公开(公告)号：US5216270A

公开(公告)日：1993-06-01

申请号：US662673

申请日：1991-02-28

申请人： Cetin Kaya ,  Howard L. Tigelaar ,  Mauzur Gill

发明人： Cetin Kaya ,  Howard L. Tigelaar ,  Mauzur Gill

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7883 ,  H01L29/7885

摘要： A non-volatile memory cell 10 can be fabricated by doping a semiconductor substrate 8 to form source 12 and drain 14 such that at least one small undoped region remains in source 12. A first insulation layer 26a is formed over the source 12 such that the thickness of the layer is less over the undoped region than the doped region while insulation regions 26b and 20 are simultaneously formed over the drain 14 and channel 16 regions. The insulation layer 26a formed above the undoped region of the source 12 is etched to form a tunnel window 28 and then a thin insulation layer is formed over the tunnel window 28. A conductive floating gate 16 is formed over a portion of the first insulation layer 26a which includes the tunnel window 28, over the channel region 16 and over a portion of the second insulation region 26b. Next, an insulation region 24 is formed over the floating gate 16 and a control gate 18 is formed over the insulation region 24. Other structures and methods are also disclosed.

摘要翻译： 可以通过掺杂半导体衬底8以形成源极12和漏极14，使得至少一个小的未掺杂区域保留在源极12中来制造非易失性存储器单元10.第一绝缘层26a形成在源极12上，使得 该层的厚度比掺杂区域少的未掺杂区域，而绝缘区域26b和20同时形成在漏极14和沟道16区域上。 形成在源极12的未掺杂区域之上的绝缘层26a被蚀刻以形成隧道窗28，然后在隧道窗28上方形成薄绝缘层。导电浮栅16形成在第一绝缘层的一部分上 26a，其包括隧道窗口28，在通道区域16上方以及第二绝缘区域26b的一部分上方。 接下来，在浮动栅极16上形成绝缘区域24，并且在绝缘区域24上形成控制栅极18.其它结构和方法也被公开。