公开(公告)号：US20160335082A1

公开(公告)日：2016-11-17

申请号：US14708767

申请日：2015-05-11

Applicant: Ceva D.S.P. Ltd.

Inventor： Roni M. SADEH ,  Noam DVORETZKI

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/345

Abstract: A logic circuit in a processor including a plurality of input registers, each for storing a vector containing data elements, a coefficient register for storing a vector containing N coefficients, an output register for storing a result vector, and an arithmetic unit configured to: obtain a pattern for selecting N data elements from the plurality of input registers, select a plurality of groups of N data elements from the plurality of input registers in parallel, wherein each group is selected in accordance with the pattern, and wherein each group is shifted with respect to a previous selected group, perform an arithmetic operation between each of the selected groups and the coefficients in parallel, and store results of the arithmetic operations in the output register.

Abstract translation: 一种处理器中的逻辑电路，包括多个输入寄存器，每个输入寄存器用于存储包含数据元素的向量，用于存储包含N个系数的向量的系数寄存器，用于存储结果向量的输出寄存器，以及用于获得 用于从多个输入寄存器中选择N个数据元素的模式，并行地从多个输入寄存器中选择多组N个数据元素，其中根据模式选择每个组，并且其中每个组与 相对于先前选择的组，在所选择的组中的每一个和并行的系数之间执行算术运算，并将算术运算的结果存储在输出寄存器中。

公开(公告)号：US20170255572A1

公开(公告)日：2017-09-07

申请号：US15062436

申请日：2016-03-07

Applicant: Ceva D.S.P. Ltd.

Inventor： Amos ROHE ,  Roni M. SADEH

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/08

CPC classification number: G06F12/1483 ,  G06F12/0826 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0875 ,  G06F2212/1032 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/1052 ,  G06F2212/6026 ,  G06F2212/622 ,  G06T1/60

Abstract: A system and method for preventing cache contention for a cache including a plurality of ways and a separate port for each way, the method including: obtaining, in a core of a processor, a multidimensional coefficient array of a multidimensional filter, and pointers to data elements from a plurality of rows of a multidimensional data array, and loading the plurality of rows into the cache, where each row is stored in a different way of the cache.