公开(公告)号：US20110205797A1

公开(公告)日：2011-08-25

申请号：US13008441

申请日：2011-01-18

申请人： Chan Ho KIM ,  Dong Kyu YOUN ,  Sang Won HWANG ,  Jin Yub LEE

发明人： Chan Ho KIM ,  Dong Kyu YOUN ,  Sang Won HWANG ,  Jin Yub LEE

IPC分类号： G11C16/08

CPC分类号： G11C8/12 ,  G11C16/0483 ,  G11C16/08

摘要： A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

摘要翻译： 非易失性存储器件包括第一垫，第二垫，第三垫，第一地址解码器，第二地址解码器和第三地址解码器。 第一垫包括第一存储块，第二垫包括第二存储块，第三块包括第三存储块。 第一地址解码器根据第一偶数地址选择第一存储块之一，第二地址解码器根据第二偶数地址或第一奇数地址选择第二存储块之一，并且第三地址解码器选择 第三存储器块根据第二奇数地址。

公开(公告)号：US20110299343A1

公开(公告)日：2011-12-08

申请号：US13151346

申请日：2011-06-02

申请人： Jin Yub LEE

发明人： Jin Yub LEE

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C16/24

摘要： A non-volatile memory device, precharge voltage control method thereof, and system including the same are provided. The non-volatile memory device includes a bit line connected with a non-volatile memory cell, a precharge voltage generation circuit configured to generate a precharge voltage during a precharge operation, and a control circuit configured to apply the precharge voltage of a second level to the bit line in response to a control signal at a first level during a precharge period in a normal read operation and to apply the precharge voltage of a fourth level to the bit line in response to the control signal at the third level during a precharge period in a verify read or erase operation.

摘要翻译： 提供了一种非易失性存储器件，其预充电电压控制方法和包括该非易失性存储器件的系统。 非易失性存储装置包括与非易失性存储单元连接的位线，预充电电压产生电路，被配置为在预充电操作期间产生预充电电压;以及控制电路，被配置为将第二电平的预充电电压施加到 在正常读取操作期间在预充电期间响应于处于第一电平的控制信号的位线，并且在预充电周期期间响应于第三电平的控制信号将第四电平的预充电电压施加到位线 在验证读取或擦除操作。