摘要:
A new method of fabricating a Flash EEPROM memory cell is achieved. Ions are optionally implanted into said semiconductor substrate to form threshold enhancement regions of the same type as the semiconductor substrate. A tunneling oxide is formed. A first conductive layer is deposited. An interpoly oxide layer is deposited. A second conductive layer is deposited. The second conductive layer, the interpoly oxide layer, the first conductive layer, and the tunneling oxide layer are patterned to form control gates and floating gates. Ions are implanted to form drain junctions. A mask protects the planned source junctions. The drain junctions are opposite type to the semiconductor substrate. Ions are implanted to form source junctions. A mask protects the drain junctions. The source junctions are opposite type to the semiconductor substrate. Ions are implanted to form channel stop junctions to complete the Flash EEPROM memory cells. The ion implantation is performed at a non-perpendicular angle with respect to the substrate. The channel stop junctions contain the source junctions. The channel stop junctions are opposite type to the semiconductor substrate. A mask protects the drain junctions.
摘要:
The present invention relates to a container (e.g., a bottle) for holding liquid therein. More particularly, the container includes a body having upper and lower ends and a recessed storage compartment formed in the lower end. The container also includes a plurality of cups removably positioned in the storage compartment. The storage compartment extends upwardly from the lower end toward the upper end of the body such that the storage compartment is recessed into the body. The storage compartment is sized and shaped such that the cups are housed completely within the storage compartment.
摘要:
A method for fabricating an STI gap fill oxide layer in a semiconductor device is provided. The method can include: forming a shallow trench for forming an STI on a semiconductor substrate; forming an STI liner oxide layer in the shallow trench for the STI; depositing an APCVD oxide layer at an upper portion of the STI liner oxide layer for an oxide layer gap fill in the shallow trench of the STI; d) performing a densifying annealing process to densify the APCVD oxide layer; and depositing an HDP-CVD oxide layer at an upper portion of the APCVD oxide layer so that the STI shallow trench is completely gap-filled.
摘要:
This invention discloses a method of manufacturing a flash EEPROM cell having a split gate structure in which source and drain regions are formed by self align method without using of an additional mask. Problems caused by that length of control gates in each cell are different from each other due to the misalignment between a mask for forming the control gate and a mask for forming source and drain regions are solved since source and drain regions are formed by self align method without using of an additional mask.
摘要:
A method and system for processing surveillance video stored on a video storage system is provided. A universal media control command is received and translated to a local control command specific to a video storage system. The surveillance video is retrieved in response to receipt of the local control command. The surveillance video can be decoded into raw video data and displayed, or be encapsulated within a universal data file. The surveillance video may be subsequently extracted from the universal data file
摘要:
A new method is provided for the creation of floating gates of a flash memory array. The floating gates of conventional flash memory devices are formed using a single polysilicon deposition followed by a single polysilicon etch. The invention provides a method that allows for the reduction in the spacing between adjacent floating gates by providing a double polysilicon deposition followed by a double polysilicon etch process. The process of the invention starts with the formation of FOX regions in a semiconductor surface; the channel regions of the devices are implanted. The first half of the floating gates of the device are formed followed by the formation of the second half of the floating gates of the device. The control gate of the device is formed as a last step of the processes of the invention.