Flash memory cell structure with improved channel punch-through characteristics
    1.
    发明授权
    Flash memory cell structure with improved channel punch-through characteristics 失效
    闪存单元结构具有改善的通道穿透特性

    公开(公告)号:US06284603B1

    公开(公告)日:2001-09-04

    申请号:US09614555

    申请日:2000-07-12

    IPC分类号: H01L218247

    摘要: A new method of fabricating a Flash EEPROM memory cell is achieved. Ions are optionally implanted into said semiconductor substrate to form threshold enhancement regions of the same type as the semiconductor substrate. A tunneling oxide is formed. A first conductive layer is deposited. An interpoly oxide layer is deposited. A second conductive layer is deposited. The second conductive layer, the interpoly oxide layer, the first conductive layer, and the tunneling oxide layer are patterned to form control gates and floating gates. Ions are implanted to form drain junctions. A mask protects the planned source junctions. The drain junctions are opposite type to the semiconductor substrate. Ions are implanted to form source junctions. A mask protects the drain junctions. The source junctions are opposite type to the semiconductor substrate. Ions are implanted to form channel stop junctions to complete the Flash EEPROM memory cells. The ion implantation is performed at a non-perpendicular angle with respect to the substrate. The channel stop junctions contain the source junctions. The channel stop junctions are opposite type to the semiconductor substrate. A mask protects the drain junctions.

    摘要翻译: 实现了制造闪存EEPROM存储单元的新方法。 任选地将离子注入到所述半导体衬底中以形成与半导体衬底相同类型的阈值增强区域。 形成隧道氧化物。 沉积第一导电层。 沉积了多晶氧化层。 沉积第二导电层。 将第二导电层,多晶硅氧化物层,第一导电层和隧道氧化物层图案化以形成控制栅极和浮栅。 植入离子以形成排水路口。 面罩保护计划的源路口。 漏极结与半导体衬底相反。 植入离子以形成源结。 掩模保护排水路口。 源极结与半导体衬底相反。 离子被植入以形成通道停止接头以完成闪存EEPROM存储单元。 以相对于衬底的非垂直角度执行离子注入。 通道停止点包含源路口。 通道停止接头与半导体衬底相反。 面罩保护排水路口。

    LIQUID CONTAINER EQUIPPED WITH DRINKING CUPS
    2.
    发明申请
    LIQUID CONTAINER EQUIPPED WITH DRINKING CUPS 审中-公开
    装有饮料杯的液体容器

    公开(公告)号:US20110253712A1

    公开(公告)日:2011-10-20

    申请号:US12761754

    申请日:2010-04-16

    申请人: Sung Rae Kim

    发明人: Sung Rae Kim

    IPC分类号: B65D21/02

    CPC分类号: A45F3/46 A45F3/18 A45F3/20

    摘要: The present invention relates to a container (e.g., a bottle) for holding liquid therein. More particularly, the container includes a body having upper and lower ends and a recessed storage compartment formed in the lower end. The container also includes a plurality of cups removably positioned in the storage compartment. The storage compartment extends upwardly from the lower end toward the upper end of the body such that the storage compartment is recessed into the body. The storage compartment is sized and shaped such that the cups are housed completely within the storage compartment.

    摘要翻译: 本发明涉及一种用于在其中保持液体的容器(例如,瓶子)。 更具体地,容器包括具有上端和下端的主体和形成在下端的凹陷的储存室。 容器还包括可移除地定位在储藏室中的多个杯子。 储物室从主体的下端朝向上端部向上延伸,使得储藏室凹进体内。 储存室的尺寸和形状使得杯子完全容纳在储藏室内。

    Method for fabricating STI gap fill oxide layer in semiconductor devices
    3.
    发明授权
    Method for fabricating STI gap fill oxide layer in semiconductor devices 失效
    在半导体器件中制造STI间隙填充氧化物层的方法

    公开(公告)号:US07538009B2

    公开(公告)日:2009-05-26

    申请号:US11616305

    申请日:2006-12-27

    申请人: Sung Rae Kim

    发明人: Sung Rae Kim

    IPC分类号: H01L21/20

    摘要: A method for fabricating an STI gap fill oxide layer in a semiconductor device is provided. The method can include: forming a shallow trench for forming an STI on a semiconductor substrate; forming an STI liner oxide layer in the shallow trench for the STI; depositing an APCVD oxide layer at an upper portion of the STI liner oxide layer for an oxide layer gap fill in the shallow trench of the STI; d) performing a densifying annealing process to densify the APCVD oxide layer; and depositing an HDP-CVD oxide layer at an upper portion of the APCVD oxide layer so that the STI shallow trench is completely gap-filled.

    摘要翻译: 提供了一种在半导体器件中制造STI间隙填充氧化物层的方法。 该方法可以包括:在半导体衬底上形成用于形成STI的浅沟槽; 在STI的浅沟槽中形成STI衬垫氧化物层; 在STI衬垫氧化物层的上部沉积APCVD氧化物层,以便在STI的浅沟槽中填充氧化物层间隙; d)进行致密退火工艺以使APCVD氧化物层致密化; 以及在APCVD氧化物层的上部沉积HDP-CVD氧化物层,使得STI浅沟槽完全间隙填充。

    Method of manufacturing a flash EEPROM cell
    4.
    发明授权
    Method of manufacturing a flash EEPROM cell 失效
    制造快闪EEPROM单元的方法

    公开(公告)号:US5705416A

    公开(公告)日:1998-01-06

    申请号:US798960

    申请日:1997-02-11

    CPC分类号: H01L27/11521 H01L27/115

    摘要: This invention discloses a method of manufacturing a flash EEPROM cell having a split gate structure in which source and drain regions are formed by self align method without using of an additional mask. Problems caused by that length of control gates in each cell are different from each other due to the misalignment between a mask for forming the control gate and a mask for forming source and drain regions are solved since source and drain regions are formed by self align method without using of an additional mask.

    摘要翻译: 本发明公开了一种制造具有分离栅极结构的快闪EEPROM单元的方法,其中源极和漏极区域通过自对准方法形成而不使用附加掩模。 由于源极和漏极区域是通过自对准方法形成的,所以由于用于形成栅极和漏极区域的掩模之间的不对准导致的每个单元中由该长度的控制栅极引起的问题彼此不同 而不使用额外的掩模。

    METHOD AND SYSTEM FOR MULTIPLE-CODEC SURVEILLANCE VIDEO STORAGE AND RETRIEVAL
    5.
    发明申请
    METHOD AND SYSTEM FOR MULTIPLE-CODEC SURVEILLANCE VIDEO STORAGE AND RETRIEVAL 审中-公开
    多编解码器监控视频存储和检索的方法与系统

    公开(公告)号:US20080218590A1

    公开(公告)日:2008-09-11

    申请号:US11683960

    申请日:2007-03-08

    IPC分类号: H04N7/18

    摘要: A method and system for processing surveillance video stored on a video storage system is provided. A universal media control command is received and translated to a local control command specific to a video storage system. The surveillance video is retrieved in response to receipt of the local control command. The surveillance video can be decoded into raw video data and displayed, or be encapsulated within a universal data file. The surveillance video may be subsequently extracted from the universal data file

    摘要翻译: 提供了一种用于处理存储在视频存储系统上的监视视频的方法和系统。 通用媒体控制命令被接收并转换为特定于视频存储系统的本地控制命令。 响应于本地控制命令的接收,检索监视视频。 监控视频可以解码为原始视频数据并显示,或封装在通用数据文件中。 可以随后从通用数据文件中提取监视视频

    Flash memory array structure with reduced bit-line pitch
    6.
    发明授权
    Flash memory array structure with reduced bit-line pitch 失效
    闪存阵列结构具有降低的位线间距

    公开(公告)号:US06329245B1

    公开(公告)日:2001-12-11

    申请号:US09467116

    申请日:1999-12-20

    IPC分类号: H01L218247

    CPC分类号: H01L27/11521 H01L27/115

    摘要: A new method is provided for the creation of floating gates of a flash memory array. The floating gates of conventional flash memory devices are formed using a single polysilicon deposition followed by a single polysilicon etch. The invention provides a method that allows for the reduction in the spacing between adjacent floating gates by providing a double polysilicon deposition followed by a double polysilicon etch process. The process of the invention starts with the formation of FOX regions in a semiconductor surface; the channel regions of the devices are implanted. The first half of the floating gates of the device are formed followed by the formation of the second half of the floating gates of the device. The control gate of the device is formed as a last step of the processes of the invention.

    摘要翻译: 提供了一种用于创建闪存阵列的浮动栅极的新方法。 常规闪存器件的浮动栅极是使用单个多晶硅沉积形成的,随后是单个多晶硅蚀刻。 本发明提供一种方法,其允许通过提供双重多晶硅沉积以及双重多晶硅蚀刻工艺来减小相邻浮栅之间的间距。 本发明的过程开始于在半导体表面中形成FOX区域; 植入通道区域。 形成装置的浮动栅极的前半部分,然后形成装置的浮动栅极的后半部分。 该装置的控制门形成为本发明方法的最后一步。