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    Programming method for non-volatile memory and non-volatile memory-based programmable logic device
    2.
    发明授权
    Programming method for non-volatile memory and non-volatile memory-based programmable logic device 有权
    非易失性存储器和非易失性存储器可编程逻辑器件的编程方法

    公开(公告)号：US07362610B1

    公开(公告)日：2008-04-22

    申请号：US11319751

    申请日：2005-12-27

    申请人： Robert M. Salter, III ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

    发明人： Robert M. Salter, III ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3418

    摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.

    摘要翻译： 一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。 分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。 在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。 如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。 在编程段期间，每个编程段中的编程电位增加。 连续段中的编程电位要么增加，要么升高到先前编程段的最终值。

    LIQUID CONTAINER EQUIPPED WITH DRINKING CUPS
    3.
    发明申请
    LIQUID CONTAINER EQUIPPED WITH DRINKING CUPS 审中-公开
    装有饮料杯的液体容器

    公开(公告)号：US20110253712A1

    公开(公告)日：2011-10-20

    申请号：US12761754

    申请日：2010-04-16

    申请人： Sung Rae Kim

    发明人： Sung Rae Kim

    IPC分类号： B65D21/02

    CPC分类号： A45F3/46 ,  A45F3/18 ,  A45F3/20

    摘要： The present invention relates to a container (e.g., a bottle) for holding liquid therein. More particularly, the container includes a body having upper and lower ends and a recessed storage compartment formed in the lower end. The container also includes a plurality of cups removably positioned in the storage compartment. The storage compartment extends upwardly from the lower end toward the upper end of the body such that the storage compartment is recessed into the body. The storage compartment is sized and shaped such that the cups are housed completely within the storage compartment.

    摘要翻译： 本发明涉及一种用于在其中保持液体的容器（例如，瓶子）。 更具体地，容器包括具有上端和下端的主体和形成在下端的凹陷的储存室。 容器还包括可移除地定位在储藏室中的多个杯子。 储物室从主体的下端朝向上端部向上延伸，使得储藏室凹进体内。 储存室的尺寸和形状使得杯子完全容纳在储藏室内。

    Method for fabricating STI gap fill oxide layer in semiconductor devices
    4.
    发明授权
    Method for fabricating STI gap fill oxide layer in semiconductor devices 失效
    在半导体器件中制造STI间隙填充氧化物层的方法

    公开(公告)号：US07538009B2

    公开(公告)日：2009-05-26

    申请号：US11616305

    申请日：2006-12-27

    申请人： Sung Rae Kim

    发明人： Sung Rae Kim

    IPC分类号： H01L21/20

    CPC分类号： H01L21/76224 ,  C23C16/045 ,  C23C16/54 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31608

    摘要： A method for fabricating an STI gap fill oxide layer in a semiconductor device is provided. The method can include: forming a shallow trench for forming an STI on a semiconductor substrate; forming an STI liner oxide layer in the shallow trench for the STI; depositing an APCVD oxide layer at an upper portion of the STI liner oxide layer for an oxide layer gap fill in the shallow trench of the STI; d) performing a densifying annealing process to densify the APCVD oxide layer; and depositing an HDP-CVD oxide layer at an upper portion of the APCVD oxide layer so that the STI shallow trench is completely gap-filled.

    摘要翻译： 提供了一种在半导体器件中制造STI间隙填充氧化物层的方法。 该方法可以包括：在半导体衬底上形成用于形成STI的浅沟槽; 在STI的浅沟槽中形成STI衬垫氧化物层; 在STI衬垫氧化物层的上部沉积APCVD氧化物层，以便在STI的浅沟槽中填充氧化物层间隙; d）进行致密退火工艺以使APCVD氧化物层致密化; 以及在APCVD氧化物层的上部沉积HDP-CVD氧化物层，使得STI浅沟槽完全间隙填充。

    Memory device with multiple memory layers of local charge storage
    5.
    发明授权
    Memory device with multiple memory layers of local charge storage 失效
    具有多个本地电荷存储层的存储器件

    公开(公告)号：US07098505B1

    公开(公告)日：2006-08-29

    申请号：US10939132

    申请日：2004-09-09

    申请人： Kyung Joon Han ,  Sung-Rae Kim ,  Robert Broze

    发明人： Kyung Joon Han ,  Sung-Rae Kim ,  Robert Broze

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G11C16/0458 ,  G11C16/0475 ,  H01L21/28282

    摘要： A multiple memory layer device has a plurality of stacked memory layers. Each of the memory layers has: a charge generating layer of p-type semiconductor material with a plurality of n-type diffusion regions; an insulating layer disposed over the charge generating layer; a charge storing layer disposed over the insulating layer; and another insulating layer disposed over the charge storing layer. A gate is disposed over the top insulting layer in the uppermost memory layer in the plurality of stacked memory layers.

    摘要翻译： 多存储层设备具有多个堆叠的存储器层。 每个存储层具有：具有多个n型扩散区的p型半导体材料的电荷产生层; 设置在所述电荷产生层上的绝缘层; 设置在所述绝缘层上的电荷存储层; 以及设置在电荷存储层上的另一绝缘层。 栅极设置在多个层叠的存储层中的最上层存储层中的顶部绝缘层上。

    Programming method for non-volatile memory and non-volatile memory-based programmable logic device
    7.
    发明授权
    Programming method for non-volatile memory and non-volatile memory-based programmable logic device 有权
    非易失性存储器和非易失性存储器可编程逻辑器件的编程方法

    公开(公告)号：US07623390B2

    公开(公告)日：2009-11-24

    申请号：US12024867

    申请日：2008-02-01

    申请人： Robert M. Salter, III ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

    发明人： Robert M. Salter, III ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

    IPC分类号： G11C16/06

    CPC分类号： G11C16/3418

    摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.

    摘要翻译： 一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。 分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。 在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。 如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。 在编程段期间，每个编程段中的编程电位增加。 连续段中的编程电位要么增加，要么升高到先前编程段的最终值。

    PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-BASED PROGRAMMABLE LOGIC DEVICE
    8.
    发明申请
    PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-BASED PROGRAMMABLE LOGIC DEVICE 有权
    非易失性存储器和非易失性存储器可编程逻辑器件的编程方法

    公开(公告)号：US20080137436A1

    公开(公告)日：2008-06-12

    申请号：US12024867

    申请日：2008-02-01

    申请人： Robert M. Salter ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

    发明人： Robert M. Salter ,  Kyung Joon Han ,  Sung-Rae Kim ,  Nigel Chan

    IPC分类号： G11C16/34

    CPC分类号： G11C16/3418

    摘要： A method for programming a flash memory cell comprises providing input data to the flash cell and providing a segmented programming pulse to the flash memory cell. The segmented programming pulse includes programming segments, each successive programming segment including a programming potential higher than the programming potential used in a previous programming segment, each programming segment followed by a zero-potential compare segment. The output of the flash memory cell is compared with the input data during the compare segment after each programming segment. The segmented programming pulse is terminated if the output of the flash memory cell matches the input data. The programming potential in each programming segment is increased during the programming segment. The programming potential in successive segments is either is increased or stepped up to the final value of the previous programming segment.

    摘要翻译： 一种用于对闪存单元进行编程的方法包括向闪存单元提供输入数据，并向闪存单元提供分段编程脉冲。 分段编程脉冲包括编程段，每个连续编程段包括高于先前编程段中使用的编程电位的编程电位，每个编程段后跟零电位比较段。 在每个编程段之后的比较段期间，将闪存单元的输出与输入数据进行比较。 如果闪存单元的输出与输入数据匹配，则分段编程脉冲终止。 在编程段期间，每个编程段中的编程电位增加。 连续段中的编程电位要么增加，要么升高到先前编程段的最终值。

    Method of manufacturing a flash EEPROM cell
    9.
    发明授权
    Method of manufacturing a flash EEPROM cell 失效
    制造快闪EEPROM单元的方法

    公开(公告)号：US5705416A

    公开(公告)日：1998-01-06

    申请号：US798960

    申请日：1997-02-11

    申请人： Jong Oh Kim ,  Sung Rae Kim

    发明人： Jong Oh Kim ,  Sung Rae Kim

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： This invention discloses a method of manufacturing a flash EEPROM cell having a split gate structure in which source and drain regions are formed by self align method without using of an additional mask. Problems caused by that length of control gates in each cell are different from each other due to the misalignment between a mask for forming the control gate and a mask for forming source and drain regions are solved since source and drain regions are formed by self align method without using of an additional mask.

    摘要翻译： 本发明公开了一种制造具有分离栅极结构的快闪EEPROM单元的方法，其中源极和漏极区域通过自对准方法形成而不使用附加掩模。 由于源极和漏极区域是通过自对准方法形成的，所以由于用于形成栅极和漏极区域的掩模之间的不对准导致的每个单元中由该长度的控制栅极引起的问题彼此不同 而不使用额外的掩模。

    LDPC ENCODING/DECODING METHOD AND DEVICE USING SAME
    10.
    发明申请
    LDPC ENCODING/DECODING METHOD AND DEVICE USING SAME 有权
    LDPC编码/解码方法和使用相同的设备

    公开(公告)号：US20140173375A1

    公开(公告)日：2014-06-19

    申请号：US14234714

    申请日：2012-07-12

    申请人： Dong-Joon Shin ,  Sung-Rae Kim

    发明人： Dong-Joon Shin ,  Sung-Rae Kim

    IPC分类号： H03M13/11

    CPC分类号： H03M13/1148 ,  H03M13/611 ,  H03M13/618

    摘要： Disclosed are an LDPC encoding/decoding method and a device using same. The method includes the steps of: (a) generating an information bit sequence by determining information bits to be encoded from among a group of information bits; (b) generating a modified information bit sequence by inserting a preset error floor prevention bit into at least one preset position in the information bit sequence; (c) generating a parity check bit on the basis of the modified information bit sequence; and (d) performing encoding by using the modified information bit sequence and the parity check bit. According to the disclosed method, performance degradation of LDPC encoding and decoding due to an error floor phenomenon can be prevented.

    摘要翻译： 公开了LDPC编码/解码方法和使用它的装置。 该方法包括以下步骤：（a）通过从一组信息比特中确定要编码的信息比特来产生信息比特序列; （b）通过将预设的错误防止地址位插入信息位序列中的至少一个预设位置来产生修改的信息位序列; （c）基于修改的信息比特序列生成奇偶校验比特; 和（d）通过使用修改的信息比特序列和奇偶校验位进行编码。 根据所公开的方法，可以防止由于错误出现现象引起的LDPC编码和解码的性能下降。