公开(公告)号：US06284603B1

公开(公告)日：2001-09-04

申请号：US09614555

申请日：2000-07-12

申请人： Chan Tze Ho Simon ,  Tyrone Philip Stodart ,  Sung Rae Kim ,  Yung-Tao Lin

发明人： Chan Tze Ho Simon ,  Tyrone Philip Stodart ,  Sung Rae Kim ,  Yung-Tao Lin

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L21/26586 ,  H01L29/7883 ,  Y10S438/983

摘要： A new method of fabricating a Flash EEPROM memory cell is achieved. Ions are optionally implanted into said semiconductor substrate to form threshold enhancement regions of the same type as the semiconductor substrate. A tunneling oxide is formed. A first conductive layer is deposited. An interpoly oxide layer is deposited. A second conductive layer is deposited. The second conductive layer, the interpoly oxide layer, the first conductive layer, and the tunneling oxide layer are patterned to form control gates and floating gates. Ions are implanted to form drain junctions. A mask protects the planned source junctions. The drain junctions are opposite type to the semiconductor substrate. Ions are implanted to form source junctions. A mask protects the drain junctions. The source junctions are opposite type to the semiconductor substrate. Ions are implanted to form channel stop junctions to complete the Flash EEPROM memory cells. The ion implantation is performed at a non-perpendicular angle with respect to the substrate. The channel stop junctions contain the source junctions. The channel stop junctions are opposite type to the semiconductor substrate. A mask protects the drain junctions.

摘要翻译： 实现了制造闪存EEPROM存储单元的新方法。 任选地将离子注入到所述半导体衬底中以形成与半导体衬底相同类型的阈值增强区域。 形成隧道氧化物。 沉积第一导电层。 沉积了多晶氧化层。 沉积第二导电层。 将第二导电层，多晶硅氧化物层，第一导电层和隧道氧化物层图案化以形成控制栅极和浮栅。 植入离子以形成排水路口。 面罩保护计划的源路口。 漏极结与半导体衬底相反。 植入离子以形成源结。 掩模保护排水路口。 源极结与半导体衬底相反。 离子被植入以形成通道停止接头以完成闪存EEPROM存储单元。 以相对于衬底的非垂直角度执行离子注入。 通道停止点包含源路口。 通道停止接头与半导体衬底相反。 面罩保护排水路口。

公开(公告)号：US06703659B2

公开(公告)日：2004-03-09

申请号：US10338221

申请日：2003-01-08

申请人： Tze Ho Semon Chan ,  Yung-Tao Lin

发明人： Tze Ho Semon Chan ,  Yung-Tao Lin

IPC分类号： H01L2976

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/7885

摘要： A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions. The angled pocket junctions are implanted at a non-perpendicular angle with respect to the semiconductor substrate and are counter-doped to the drain junctions. Ions are implanted to form source junctions where the junctions are deeper and less abrupt than the drain junctions to complete the Flash EEPROM memory cells in the integrated circuit device.

摘要翻译： 实现了一种制造和编程和擦除闪存EEPROM存储单元的新方法。 提供半导体衬底。 形成覆盖所述半导体衬底的隧道氧化物层。 沉积在隧道氧化物层上的第一多晶硅层。 沉积在第一多晶硅层上的多晶硅层。 第二多晶硅层沉积在层间氧化物层的上方。 对第二多晶硅层，多晶硅氧化物层，第一多晶硅层和隧道氧化物层进行图案化以形成用于计划的闪存EEPROM存储单元的控制栅极和浮置栅极。 离子被植入以形成半导体衬底中计划的闪存EEPROM存储单元的漏极结，其中漏极接点较浅而突然。 植入离子以形成与排水结相邻的倾斜的袋结。 成角度的凹穴接合部以相对于半导体衬底的非垂直角注入，并且与掺杂的漏极结相反。 离子被植入以形成其中结点比漏极结更深并且不太突然的源结，以完成集成电路器件中的闪存EEPROM存储单元。

公开(公告)号：US06518122B1

公开(公告)日：2003-02-11

申请号：US09465227

申请日：1999-12-17

申请人： Tze Ho Simon Chan ,  Yung-Tao Lin

发明人： Tze Ho Simon Chan ,  Yung-Tao Lin

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/7885

摘要： A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions. The angled pocket junctions are implanted at a non-perpendicular angle with respect to the semiconductor substrate and are counter-doped to the drain junctions. Ions are implanted to form source junctions where the junctions are deeper and less abrupt than the drain junctions to complete the Flash EEPROM memory cells in the integrated circuit device.

摘要翻译： 实现了一种制造和编程和擦除闪存EEPROM存储单元的新方法。 提供半导体衬底。 形成覆盖所述半导体衬底的隧道氧化物层。 沉积在隧道氧化物层上的第一多晶硅层。 沉积在第一多晶硅层上的多晶硅层。 第二多晶硅层沉积在层间氧化物层的上方。 对第二多晶硅层，多晶硅氧化物层，第一多晶硅层和隧道氧化物层进行图案化以形成用于计划的闪存EEPROM存储单元的控制栅极和浮置栅极。 离子被植入以形成半导体衬底中计划的闪存EEPROM存储单元的漏极结，其中漏极接点较浅而突然。 植入离子以形成与排水结相邻的倾斜的袋结。 成角度的凹穴接合部以相对于半导体衬底的非垂直角注入，并且与掺杂的漏极结相反。 离子被植入以形成其中结点比漏极结更深并且不太突然的源结，以完成集成电路器件中的闪存EEPROM存储单元。

公开(公告)号：US5821765A

公开(公告)日：1998-10-13

申请号：US900013

申请日：1997-07-24

申请人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

发明人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： H01L23/544 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively suicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

摘要翻译： 用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。 实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。 连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。 测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。 用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。 第二实施例选择性地使源极 - 漏极电阻器的暴露部分自动化，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。 通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

公开(公告)号：US08110881B2

公开(公告)日：2012-02-07

申请号：US11863130

申请日：2007-09-27

申请人： Ya-Chen Kao ,  Chun-Jung Lin ,  Yu-Jen Wang ,  Hsu-Chen Cheng ,  Feng-Jia Shiu ,  Yung-Tao Lin

发明人： Ya-Chen Kao ,  Chun-Jung Lin ,  Yu-Jen Wang ,  Hsu-Chen Cheng ,  Feng-Jia Shiu ,  Yung-Tao Lin

IPC分类号： H01L29/82

CPC分类号： H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/16 ,  H01L43/08

摘要： A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit.

摘要翻译： MRAM单元结构包括底电极; 设置在所述底部电极上的磁性隧道结单元; 设置在磁隧道结单元上的顶电极; 以及设置在所述顶部电极上的阻挡层，其中所述阻挡层比所述磁性隧道结单元宽，以防止在触点和所述磁性隧道结单元之间形成短路。

公开(公告)号：US20090085132A1

公开(公告)日：2009-04-02

申请号：US11863130

申请日：2007-09-27

申请人： Ya Chen Kao ,  Chun-Jung Lin ,  Yu-Jen Wang ,  Hsu-Chen Cheng ,  Feng-Jia Shiu ,  Yung-Tao Lin

发明人： Ya Chen Kao ,  Chun-Jung Lin ,  Yu-Jen Wang ,  Hsu-Chen Cheng ,  Feng-Jia Shiu ,  Yung-Tao Lin

IPC分类号： H01L29/82

CPC分类号： H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/16 ,  H01L43/08

摘要： A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit.

摘要翻译： MRAM单元结构包括底电极; 设置在所述底部电极上的磁性隧道结单元; 设置在磁隧道结单元上的顶电极; 以及设置在所述顶部电极上的阻挡层，其中所述阻挡层比所述磁性隧道结单元宽，以防止在触点和所述磁性隧道结单元之间形成短路。

公开(公告)号：US20080006868A1

公开(公告)日：2008-01-10

申请号：US11483916

申请日：2006-07-10

申请人： Te-Hsun Hsu ,  Yung-Tao Lin ,  Derek Lin ,  Jack Yeh

发明人： Te-Hsun Hsu ,  Yung-Tao Lin ,  Derek Lin ,  Jack Yeh

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11558

摘要： A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source/drain region of the transistor is connected to the first doped region of the first capacitor.

摘要翻译： 提供了一种非易失性存储单元及其制造方法。 非易失性存储单元包括在半导体衬底上的浮动栅极，包括第一板，浮栅及其之间的电介质的第一电容器，包括第二板，浮栅及其之间的电介质的第二电容器， 第三电容器，包括连接到浮置栅极的第三板和第四板，其中第三板和第四板形成在半导体衬底上的金属化层中。 第一电容器的第一板包括在半导体衬底中的第一掺杂区和第二掺杂区。 非易失性存储单元还包括晶体管，其包括在半导体衬底上的栅电极，其中晶体管的源/漏区连接到第一电容器的第一掺杂区。

公开(公告)号：US06760258B2

公开(公告)日：2004-07-06

申请号：US10338220

申请日：2003-01-08

申请人： Tze Ho Simon Chan ,  Yung-Tao Lin

发明人： Tze Ho Simon Chan ,  Yung-Tao Lin

IPC分类号： G11C1604

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/7885

摘要： A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A tunneling oxide layer is formed overlying a semiconductor substrate. A first polysilicon layer, an interpoly oxide layer and then a second polysilicon layer are deposited. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions. The angled pocket junctions are implanted at a non-perpendicular angle with respect to the semiconductor substrate and are counter-doped to the drain junctions. Ions are implanted to form source junctions that are deeper and less abrupt than the drain junctions.

摘要翻译： 实现了一种制造和编程和擦除闪存EEPROM存储单元的新方法。 形成覆盖在半导体衬底上的隧穿氧化层。 沉积第一多晶硅层，多晶硅层，然后沉积第二多晶硅层。 对第二多晶硅层，多晶硅氧化物层，第一多晶硅层和隧道氧化物层进行图案化以形成用于计划的闪存EEPROM存储单元的控制栅极和浮置栅极。 离子被植入以形成漏极结，其中漏极结较浅并且突然。 植入离子以形成与排水结相邻的倾斜的袋结。 成角度的凹穴接合部以相对于半导体衬底的非垂直角注入，并且与掺杂的漏极结相反。 植入离子以形成比排水接头更深且更不突出的源结。

公开(公告)号：US6147008A

公开(公告)日：2000-11-14

申请号：US443421

申请日：1999-11-19

申请人： Siow Lee Chwa ,  Ying Jin ,  Yung-Tao Lin

发明人： Siow Lee Chwa ,  Ying Jin ,  Yung-Tao Lin

IPC分类号： H01L21/8247 ,  H01L21/265 ,  H01L21/31 ,  H01L21/316 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/823462 ,  Y10S438/981

摘要： A new method is provided for the creation of an oxide layer that contains three different thicknesses. A first layer of oxide is grown on the surface of a substrate; a first layer of photoresist is deposited and patterned thereby partially exposing the surface of the underlying first layer of oxide. A nitrogen implant is performed into the surface of the underlying substrate; the photoresist mask of the first layer of photoresist is removed. A second layer of photoresist is deposited and patterned, the first layer of oxide is removed from above and surrounding the implanted regions of the substrate. The second mask of resist is removed. The first layer of oxide is reduced in thickness, its thickness is restored to a first thickness by a blanket growth of a second layer of oxide over the exposed surface of the substrate (where no ion implant has been performed) to a third thickness, over the surface of the substrate where the ion implant has been performed to a second thickness and over the surface of the first layer of oxide thereby restoring this layer of oxide to its original first thickness.

摘要翻译： 提供了一种新方法，用于产生含有三种不同厚度的氧化物层。 在衬底的表面上生长第一层氧化物; 沉积和图案化第一层光致抗蚀剂，从而部分地暴露下面的第一层氧化物的表面。 在下面的基底的表面上进行氮注入; 去除第一层光致抗蚀剂的光致抗蚀剂掩模。 沉积和图案化第二层光致抗蚀剂，从上方去除第一层氧化物并围绕衬底的注入区域。 抗蚀剂的第二个掩模被去除。 第一层氧化物的厚度减小，其厚度通过在衬底的暴露表面（其中没有进行离子注入）到第三厚度的第二层氧化物的覆盖生长而恢复到第一厚度，超过 已经进行离子注入的衬底的表面达到第二厚度并且在第一氧化物层的表面上，从而将该氧化物层恢复到其原始的第一厚度。

公开(公告)号：US07514740B2

公开(公告)日：2009-04-07

申请号：US11483916

申请日：2006-07-10

申请人： Te-Hsun Hsu ,  Yung-Tao Lin ,  Derek Lin ,  Jack Yeh

发明人： Te-Hsun Hsu ,  Yung-Tao Lin ,  Derek Lin ,  Jack Yeh

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/115 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11558

摘要： A non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source/drain region of the transistor is connected to the first doped region of the first capacitor.

摘要翻译： 非易失性存储单元包括在半导体衬底上的浮动栅极，包括第一板，浮置栅极和其间的电介质的第一电容器，包括第二板，浮栅及其间的电介质的第二电容器， 第三电容器，包括连接到浮置栅极的第三板和第四板，其中第三板和第四板形成在半导体衬底上的金属化层中。 第一电容器的第一板包括半导体衬底中的第一掺杂区和第二掺杂区。 非易失性存储单元还包括晶体管，其包括在半导体衬底上的栅电极，其中晶体管的源/漏区连接到第一电容器的第一掺杂区。