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    Semiconductor memory device having a block selection function with low power consumptions
    2.
    发明授权
    Semiconductor memory device having a block selection function with low power consumptions 失效
    具有低功耗的块选择功能的半导体存储器件

    公开(公告)号：US5327389A

    公开(公告)日：1994-07-05

    申请号：US918770

    申请日：1992-07-27

    申请人： Yong-Sik Seok ,  Dong-Sun Min ,  Dong-Soo Jun ,  Jae-Gu Roh

    发明人： Yong-Sik Seok ,  Dong-Sun Min ,  Dong-Soo Jun ,  Jae-Gu Roh

    IPC分类号： G11C11/41 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C7/00

    CPC分类号： G11C8/12

    摘要： A semiconductor memory device divided into a number of main blocks each main block having a number of subblocks selects a single main block and enables the subblocks of the selected main block, so as to reduce the power consumptions. The semiconductor memory device includes a block selector for selecting one of the main blocks in response to row address signals, a number of first boost circuits for selecting the subblocks of the selected main block in response to the row address signals, and a number of second boost circuits adapted to be disabled in response to the row address signals.

    摘要翻译： 分割为多个主块的半导体存储器件，具有多个子块的每个主块选择单个主块并使能所选主块的子块，以便减少功耗。 半导体存储器件包括：块选择器，用于响应于行地址信号选择主块之一;多个第一升压电路，用于响应于行地址信号选择所选主块的子块;以及多个第二 适于响应于行地址信号被禁用的升压电路。

    Self-refresh method and refresh control circuit of a semiconductor memory device
    3.
    发明授权
    Self-refresh method and refresh control circuit of a semiconductor memory device 失效
    半导体存储器件的自刷新方法和刷新控制电路

    公开(公告)号：US5583818A

    公开(公告)日：1996-12-10

    申请号：US358120

    申请日：1994-12-19

    申请人： Jei-Hwan You ,  Dong-Soo Jun

    发明人： Jei-Hwan You ,  Dong-Soo Jun

    IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/406

    摘要： A self-refresh method and refresh control circuit of a semiconductor memory device, wherein after the self-refresh mode starts, the burst refresh mode is performed prior to the self-refresh mode; or the self-refresh mode is performed immediately after going into the self-refresh mode, and the burst refresh mode is performed at the completion of the self-refresh mode, and then the burst refresh mode is converted to the normal access mode; or the burst refresh mode is performed before and after the self-refresh mode, thereby shortening a refresh regulation time and securing a stable refresh of the memory cells.

    摘要翻译： 一种半导体存储器件的自刷新方法和刷新控制电路，其中在自刷新模式开始之后，在自刷新模式之前执行突发刷新模式; 或者在进入自刷新模式后立即执行自刷新模式，并且在完成自刷新模式时执行突发刷新模式，然后将突发刷新模式转换为正常访问模式; 或者在自刷新模式之前和之后执行突发刷新模式，从而缩短刷新调节时间并确保存储单元的稳定刷新。

    Sense amplifier for high performance dram
    4.
    发明授权
    Sense amplifier for high performance dram 失效
    感应放大器，用于高性能播放

    公开(公告)号：US4855628A

    公开(公告)日：1989-08-08

    申请号：US120985

    申请日：1987-11-16

    申请人： Dong-Soo Jun

    发明人： Dong-Soo Jun

    IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C11/4091 ,  G11C11/4094 ,  H03F3/00

    CPC分类号： G11C11/4094 ,  G11C11/4091

    摘要： A sense amplifier and high performance DRAM, in combination, has in the DRAM at least one row of memory cells, whereby the memory cells of the row may be arranged in respective columns with memory cells of other rows. Each of the memory cells has a transistor and a capacitor connected serially between one of bit lines successively along the row and a fixed voltage source. Word lines are respectively connected to gates of the transistors of the memory cells for activating the memory cell selectively according to row address. The sense amplifier has a cross-coupled bistable flip-flop connecting the bit lines to each other in the row. A latch transistor connected to the flip-flop detects and amplifies a voltage difference between the bit lines. The bit lines are equalized and precharged with a reference voltage in response to a clock control signal. A cross-coupled pair of transistors also connecting the bit lines to each other transfer a charging voltage to the bit lines. A power-supply level voltage is supplied under the control of first and second control clock signals and boosted to a higher level charging voltage under the control of a third control clock signal, whereby the storage capacitors of the memory cells are charged to the higher voltage.

    摘要翻译： 组合的感测放大器和高性能DRAM在DRAM中至少存在一行存储器单元，由此该行的存储单元可以被布置在具有其他行的存储器单元的相应列中。 每个存储单元具有晶体管和电容器，其沿着行连续地位于一列位线和固定电压源之间。 字线分别连接到存储器单元的晶体管的栅极，用于根据行地址选择性地激活存储器单元。 读出放大器具有交叉耦合双稳态触发器，将该行中的位线相互连接。 连接到触发器的锁存晶体管检测并放大位线之间的电压差。 位线被均衡并且响应于时钟控制信号而用参考电压预充电。 也将位线彼此连接的交叉耦合对晶体将充电电压传送到位线。 在第一和第二控制时钟信号的控制下提供电源电平电压，并在第三控制时钟信号的控制下升压到较高电平的充电电压，从而将存储单元的存储电容器充电到较高的电压 。