公开(公告)号：US6127203A

公开(公告)日：2000-10-03

申请号：US304953

申请日：1999-05-05

申请人： Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

发明人： Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

IPC分类号： H01L21/58 ,  H01L21/324

CPC分类号： H01L24/83 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/351

摘要： This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.

摘要翻译： 本发明涉及将集成电路（IC）安装到多芯片模块（MCM）或基板上。 更具体地，它提供了一种将半导体管芯如汞碲化镉（MCT）的薄片安装到硅半导体衬底，读出集成电路（ROIC），使用热塑性材料以减少MCT上的应力的方法， 通过不匹配的热膨胀系数（CTE）。 该过程提供了在诸如MCT的材料上的红外光电检测器阵列，其将使用针对FPAs的垂直集成光电二极管（VIP）方法安装到读出集成电路（ROIC），同时允许CdTe用于表面钝化的双面相互扩散 以减少暗电流并提高性能，而没有与高温过程中热膨胀系数不匹配相关的问题。

公开(公告)号：US5959340A

公开(公告)日：1999-09-28

申请号：US707815

申请日：1996-08-30

申请人： Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

发明人： Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

IPC分类号： H01L21/58 ,  H01L31/00

CPC分类号： H01L24/83 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/351

摘要： This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.