公开(公告)号：US12132026B2

公开(公告)日：2024-10-29

申请号：US18685871

申请日：2022-10-18

申请人： NIPPON STEEL Chemical & Material Co., Ltd. ,  NIPPON MICROMETAL CORPORATION

发明人： Tomohiro Uno ,  Tetsuya Oyamada ,  Daizo Oda ,  Motoki Eto

IPC分类号： H01L23/00 ,  G01N23/203 ,  G01N23/2276

CPC分类号： H01L24/45 ,  H01L24/43 ,  G01N23/203 ,  G01N23/2276 ,  G01N2223/601 ,  G01N2223/602 ,  G01N2223/611 ,  H01L2224/4321 ,  H01L2224/437 ,  H01L2224/43825 ,  H01L2224/43848 ,  H01L2224/45147 ,  H01L2224/45541 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01034 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/3512 ,  H01L2924/365

摘要： A bonding wire includes a core material of Cu or Cu alloy, and a coating layer containing a conductive metal other than Cu on a surface of the core material. In a concentration profile in a depth direction of the wire obtained, an average value of sum of a Pd concentration CPd (atomic %) and an Ni concentration CNi (atomic %) for measurement points in the coating layer is 50 atomic % or more, an average value of a ratio of CPd to CNi for measurement points in the coating layer is from 0.2 to 20 and a thickness of the coating layer is from 20 nm to 180 nm. An Au concentration CAu at a surface of the wire is from 10 atomic % to 85 atomic %. An average size of crystal grains in a circumferential direction of the wire is from 35 nm to 200 nm.

公开(公告)号：US20240258262A1

公开(公告)日：2024-08-01

申请号：US18426144

申请日：2024-01-29

申请人： THE INDIUM CORPORATION OF AMERICA

发明人： Milos Lazic ,  Richard McDonough

IPC分类号： H01L23/00 ,  H01L23/367

CPC分类号： H01L24/26 ,  H01L23/367 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/2732 ,  H01L2224/29105 ,  H01L2224/3207 ,  H01L2224/32221 ,  H01L2224/83201 ,  H01L2924/0103 ,  H01L2924/01049 ,  H01L2924/0105

摘要： Described are a double barrier system and method used to contain a thermal interface material to avoid unwanted interactions of the thermal interface material with other metals or components within a semiconductor device. In one implementation, a semiconductor assembly includes: a substrate; a heat generating device including a first surface attached to the substrate; a first barrier surrounding and in touching relation with the heat generating device; a second barrier surrounding the first barrier such that there is an area between the first barrier and the second barrier; a heat transferring device; and a thermal interface material between and in touching relation with the heat transferring device and a second surface of the heat generating device opposite the first surface.

公开(公告)号：US20240038714A1

公开(公告)日：2024-02-01

申请号：US18378733

申请日：2023-10-11

申请人： Infineon Technologies Austria AG

发明人： Alexander Heinrich

IPC分类号： H01L23/00

CPC分类号： H01L24/32 ,  H01L24/83 ,  H01L2224/32503 ,  H01L2224/8381 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3512

摘要： A method for fabricating a semiconductor device includes providing a die with a metallization layer including a first metal with a high melting point; providing a die carrier including a second metal with a high melting point; providing a solder material including a third metal with a low melting point; providing a layer of a fourth metal with a high melting point on the semiconductor die or the die carrier; and soldering the semiconductor die to the die carrier and creating: a first intermetallic compound between the semiconductor die and the die carrier and including the first metal and the third metal; a second intermetallic compound between the first intermetallic compound and the die carrier and including the second metal and the third metal; and precipitates of a third intermetallic compound between the first intermetallic compound and the second intermetallic compound and including the third metal and the fourth metal.

公开(公告)号：US11705413B2

公开(公告)日：2023-07-18

申请号：US17549901

申请日：2021-12-14

申请人： MEDIATEK INC.

发明人： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC分类号： H01L27/14 ,  H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

CPC分类号： H01L23/66 ,  H01L23/3672 ,  H01L23/3733 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01Q1/02 ,  H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/18161

摘要： A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US11694960B2

公开(公告)日：2023-07-04

申请号：US17410716

申请日：2021-08-24

申请人： Intel Corporation

发明人： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18 ,  H01L23/532 ,  H01L25/18 ,  H05K3/34

CPC分类号： H01L23/5381 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/53238 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H05K1/185 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/171 ,  H01L2224/1703 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/8147 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/81481 ,  H01L2924/00014 ,  H01L2224/81487 ,  H01L2924/04953 ,  H01L2224/81487 ,  H01L2924/04941 ,  H01L2224/81466 ,  H01L2924/01074 ,  H01L2224/81463 ,  H01L2924/01072 ,  H01L2224/81479 ,  H01L2924/00014 ,  H01L2224/8147 ,  H01L2924/00014 ,  H01L2224/81472 ,  H01L2924/00014 ,  H01L2224/81484 ,  H01L2924/00014 ,  H01L2224/81487 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2224/81487 ,  H01L2924/0481 ,  H01L2924/01029 ,  H01L2224/81487 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2224/171 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US11688612B2

公开(公告)日：2023-06-27

申请号：US15846014

申请日：2017-12-18

申请人： STATS ChipPAC Pte. Ltd.

发明人： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo ,  HeeJo Chi

IPC分类号： H01L21/56 ,  H01L21/683 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L23/552

CPC分类号： H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05552 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/4816 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00014 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/0105 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/1532 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/0002 ,  H01L2224/05552 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

公开(公告)号：US20190232438A1

公开(公告)日：2019-08-01

申请号：US16223952

申请日：2018-12-18

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： HIROHISA HINO ,  NAOMICHI OHASHI ,  YASUHIRO SUZUKI ,  KOSO MATSUNO

IPC分类号： B23K35/362 ,  B23K35/02 ,  B23K35/26 ,  C22C13/02 ,  H05K1/18 ,  H01L23/00 ,  H05K3/34

CPC分类号： B23K35/362 ,  B23K35/025 ,  B23K35/262 ,  B23K2101/40 ,  B23K2101/42 ,  C22C13/02 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/81815 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/069 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/3457 ,  H05K3/3494 ,  H05K2201/10636 ,  H05K2201/10734

摘要： Provided herein is a solder paste having low viscosity and easy coatability, and that provides high reinforcement for electronic components while satisfying both high room-temperature adhesion and high repairability, and forming a cured product of excellent properties, for example, high insulation against humidity. Amount structure including an electronic component mounted with the solder paste is also provided. The solder paste contains a solder powder and a flux. The flux contains an epoxy resin, a reactive diluent, a curing agent, an organic acid, and a rubber modified epoxy resin. The reactive diluent contains a compound having two or more epoxy groups, and has a viscosity of 150 mPa·s or more and 700 mPa·s or less. The reactive diluent has a total chlorine content of 0.5 weight % or less, and is contained in a proportion of 5 weight % or more and 45 weight % or less with respect to a total weight of the flux.

公开(公告)号：US20190027455A1

公开(公告)日：2019-01-24

申请号：US16137683

申请日：2018-09-21

申请人： Renesas Electronics Corporation

发明人： SHINYA SUZUKI ,  Kiichi Makuta

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L23/498

CPC分类号： H01L24/17 ,  G02F1/13306 ,  G02F1/13452 ,  H01L23/49811 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0292 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13644 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/9211 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/013 ,  H01L2924/04941 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15788 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00014

摘要： To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.

公开(公告)号：US10062657B2

公开(公告)日：2018-08-28

申请号：US15518219

申请日：2015-10-09

申请人： ISHIHARA CHEMICAL CO., LTD.

发明人： Shoya Iuchi ,  Masaru Hatabe

IPC分类号： H01L23/00 ,  H05K3/34

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H05K3/34 ,  H01L2924/014 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01047

摘要： In order to manufacture an alloy bump, a resist pattern having openings which expose a substrate is formed on the substrate, an under-bump metal is formed on the substrate inside the openings, a first plating film is formed on the under-bump metal by electroplating, a second plating film containing no metal components which are contained in the first plating film is formed on the first plating film by electroplating, the resist pattern is removed, and the alloy bump is formed by heat treating the substrate to thereby alloy the first plating film and the second plating film.

公开(公告)号：US20180233448A1

公开(公告)日：2018-08-16

申请号：US15951925

申请日：2018-04-12

申请人： Invensas Corporation

发明人： Ilyas Mohammed

IPC分类号： H01L23/522 ,  H01L25/10 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/56 ,  H05K3/40

CPC分类号： H01L23/5226 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/49 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45565 ,  H01L2224/45624 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/45669 ,  H01L2224/4569 ,  H01L2224/48 ,  H01L2224/49 ,  H01L2224/73267 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/182 ,  H01L2924/191 ,  H01L2924/19107 ,  H05K3/4046 ,  H05K2201/10287 ,  H05K2203/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01049

摘要： A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.