利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.018 秒)

    Method of forming on-chip decoupling capacitor with bottom electrode layer having surface roughness
    1.
    发明授权
    Method of forming on-chip decoupling capacitor with bottom electrode layer having surface roughness 有权
    形成具有表面粗糙度的底部电极层的片上去耦电容器的方法

    公开(公告)号：US07960226B2

    公开(公告)日：2011-06-14

    申请号：US11317694

    申请日：2005-12-23

    申请人： Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

    发明人： Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/53238 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    摘要： On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling. In order to facilitate the removal of photoresist by an oxygen plasma process prior to exposing copper conductors during the capacitor stack etch, an Al hardmask can be used to protect the capacitor formed with Ta2O5 dielectric, or a W hardmask can be used to protect the capacitor formed with BST dielectric.

    摘要翻译： 公开了片上去耦电容器结构以及制造这种去耦电容器的方法。 片内去耦电容有助于在高浪涌电流条件下降低或防止电网上的L di / dt电压下降。 将一个或多个去耦电容器包含在靠近电力电网导体的芯片上减小了寄生电感，从而提供了相对于高频噪声的改进的去耦性能。 在本发明的一个实施例中，在金属互连层之间插入电容器堆叠结构。 这样的电容器堆叠可以由底部电极/屏障组成; 具有高介电常数的薄介电材料; 和顶部电极/屏障。 在替代实施例中，底部电极和/或底部金属互连层具有三维结构以增加电容器的表面积。 体现本发明的说明性方法包括制造片上去耦电容器堆叠结构并电连接电容器以提供有效的电容去耦合。 为了在电容器堆叠蚀刻期间在铜导体暴露之前通过氧​​等离子体工艺来促进光致抗蚀剂的去除，可以使用Al硬掩模来保护由Ta2O5电介质形成的电容器，或者可以使用W硬掩模来保护电容器 用BST电介质形成。

    Enhanced on-chip decoupling capacitors and method of making same
    3.
    发明授权
    Enhanced on-chip decoupling capacitors and method of making same 有权
    增强片上去耦电容及其制作方法

    公开(公告)号：US07416954B2

    公开(公告)日：2008-08-26

    申请号：US10766674

    申请日：2004-01-27

    申请人： Bruce A. Block ,  Richard Scott List

    发明人： Bruce A. Block ,  Richard Scott List

    IPC分类号： H01L21/00

    CPC分类号： H01L28/87 ,  H01L27/0805

    摘要： An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

    摘要翻译： 一种包括在电路上的金属化层之间形成的电容器的装置，所述电容器包括耦合到金属层的底部电极和耦合到金属通孔的顶部电极，其中所述电容器具有波纹侧壁轮廓。 一种方法，包括在器件结构的金属层上的多层堆叠中形成包含不同介电材料的交替层的层间电介质; 形成具有波形侧壁的通孔; 以及在通孔中形成去耦电容器叠层，其符合通孔的侧壁。

    Method of forming on-chip decoupling capacitor by selectively etching grain boundaries in electrode
    4.
    发明授权
    Method of forming on-chip decoupling capacitor by selectively etching grain boundaries in electrode 失效
    通过选择性蚀刻电极中的晶界来形成片上去耦电容的方法

    公开(公告)号：US07033882B2

    公开(公告)日：2006-04-25

    申请号：US10760080

    申请日：2004-01-15

    申请人： Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

    发明人： Bruce A. Block ,  Richard Scott List ,  Ruitao Zhang

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/8242

    CPC分类号： H01L28/75 ,  H01L21/28568 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/53238 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    摘要： On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling. In order to facilitate the removal of photoresist by an oxygen plasma process prior to exposing copper conductors during the capacitor stack etch, an Al hardmask can be used to protect the capacitor formed with Ta2O5 dielectric, or a W hardmask can be used to protect the capacitor formed with BST dielectric.

    摘要翻译： 公开了片上去耦电容器结构以及制造这种去耦电容器的方法。 片内去耦电容有助于在高浪涌电流条件下降低或防止电网上的L di / dt电压下降。 将一个或多个去耦电容器包含在靠近电力电网导体的芯片上减小了寄生电感，从而提供了相对于高频噪声的改进的去耦性能。 在本发明的一个实施例中，在金属互连层之间插入电容器堆叠结构。 这样的电容器堆叠可以由底部电极/屏障组成; 具有高介电常数的薄介电材料; 和顶部电极/屏障。 在替代实施例中，底部电极和/或底部金属互连层具有三维结构以增加电容器的表面积。 体现本发明的说明性方法包括制造片上去耦电容器堆叠结构并电连接电容器以提供有效的电容去耦合。 为了在电容器堆叠蚀刻期间在铜导体暴露之前通过氧​​等离子体工艺促进光致抗蚀剂的去除，可以使用Al硬掩模来保护由Ta 2 O 5形成的电容器 电介质或W硬掩模可用于保护由BST电介质形成的电容器。