公开(公告)号：US20130163352A1

公开(公告)日：2013-06-27

申请号：US13445155

申请日：2012-04-12

Applicant: Chang-Ho DO

Inventor： Chang-Ho DO

IPC: G11C7/10

CPC classification number: G11C29/785

Abstract: A semiconductor memory device includes a plurality of repair fuse units configured to program repair target addresses respectively for repair target memory cells, wherein at least one of the repair fuse units is programmed with data information used for different purposes from the repair target addresses, a plurality of address comparison units each configured to compare an access target address with a corresponding address of the repair target addresses and determine whether to perform a repair operation or not, and a data transfer unit configured to transfer the data information to a corresponding circuit of the semiconductor memory device.

Abstract translation: 一种半导体存储器件包括多个维修熔丝单元，其被配置为分别对维修目标存储单元编制维修目标地址，其中至少一个维修保险丝单元用与维修目标地址不同的目的使用的数据信息进行编程，多个 每个地址比较单元被配置为将访问目标地址与修复目标地址的对应地址进行比较，并且确定是否执行修复操作;以及数据传送单元，被配置为将数据信息传送到半导体的相应电路 存储设备。

公开(公告)号：US20100074035A1

公开(公告)日：2010-03-25

申请号：US12630765

申请日：2009-12-03

Applicant: Chang-Ho DO

Inventor： Chang-Ho DO

IPC: G11C7/22 ,  G11C7/00

CPC classification number: G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C2207/107

Abstract: A semiconductor memory device and method to perform a read operation and a write operation effectively. The semiconductor memory device and method includes: performing a first operation for inputting and outputting data in response to a first clock signal having a first frequency; and performing a second operation for storing and reading out the data in a core block in response to a second clock signal having a second frequency, wherein the first frequency is different from the second frequency.

Abstract translation: 一种有效执行读取操作和写入操作的半导体存储器件和方法。 半导体存储器件和方法包括：响应于具有第一频率的第一时钟信号，执行用于输入和输出数据的第一操作; 以及响应于具有第二频率的第二时钟信号执行用于存储和读出核心块中的数据的第二操作，其中所述第一频率不同于所述第二频率。

公开(公告)号：US20100008162A1

公开(公告)日：2010-01-14

申请号：US12345636

申请日：2008-12-29

Applicant: Chang-Ho DO

Inventor： Chang-Ho DO

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C7/22

Abstract: A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby enhancing an equalizing speed and an active speed while minimizing power consumption. The semiconductor memory device includes a bit line equalizing signal generating unit configured to drive an output terminal with the supply voltage during a first activation period at the beginning of the period where the bit line equalizing signal is enabled, and to drive the output terminal with the pumping voltage higher than the supply voltage during a second activation period following the first activation period, thereby outputting the bit line equalizing signal, and a bit line equalizing unit configured to equalize a bit line pair in response to the bit line equalizing signal.

Abstract translation: 半导体存储器件的位线均衡信号发生器在使能位线均衡信号的时段期间分阶段使用电源电压和泵浦电压，从而在最小化功耗的同时提高均衡速度和有效速度。 半导体存储器件包括位线均衡信号产生单元，其被配置为在位线均衡信号使能的周期的开始期间的第一激活周期期间驱动具有电源电压的输出端子，并且驱动输出端子 在第一激活周期之后的第二激活期间，高于电源电压的泵浦电压，从而输出位线均衡信号，以及位线均衡单元，其被配置为响应于位线均衡信号来均衡位线对。

公开(公告)号：US20120032734A1

公开(公告)日：2012-02-09

申请号：US13274644

申请日：2011-10-17

Applicant: Chang-Ho DO

Inventor： Chang-Ho DO

IPC: G05F1/10

CPC classification number: G05F1/465

Abstract: An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock.

Abstract translation: 半导体器件的内部电压产生电路包括：第一电压驱动器，其被配置为在内部电压端子的电平低于目标电平的期间内上拉内部电压端子;以及第二电压驱动器， 在每个周期内的预定时间内对应于外部时钟的频率的内部电压端子。

公开(公告)号：US20100103752A1

公开(公告)日：2010-04-29

申请号：US12650311

申请日：2009-12-30

Applicant: Chang-Ho DO

Inventor： Chang-Ho DO

IPC: G11C7/00

CPC classification number: G11C8/18 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C29/36

Abstract: A semiconductor memory device is capable of writing data in phase with external data to a memory cell regardless of which memory cell the data is written to. The semiconductor memory device includes a scrambler, a write selector and a read selector. The scrambler is configured to output a control signal activated when an address for accessing a memory cell of a complementary bit line is inputted. The write selector is configured to selectively transmit data of a write path in response to the control signal. The read selector is configured to selectively transmit data of a read path in response to the control signal

Abstract translation: 半导体存储器件能够将数据与外部数据同步地写入存储单元，而不管数据被写入哪个存储器单元。 半导体存储器件包括加扰器，写选择器和读选择器。 扰码器被配置为当输入用于访问互补位线的存储单元的地址时，输出激活的控制信号。 写选择器被配置为响应于控制信号选择性地发送写入路径的数据。 读选择器被配置为响应于控制信号选择性地发送读路径的数据

公开(公告)号：US20100008001A1

公开(公告)日：2010-01-14

申请号：US12347503

申请日：2008-12-31

Applicant: Chang-Ho DO

Inventor： Chang-Ho DO

IPC: H02H9/04

CPC classification number: H01L27/0251

Abstract: A semiconductor device includes a pads for receiving a reference voltage and input signals from an external device, a unit gain buffer for receiving the reference voltage as an input, input buffers for identifying a corresponding one of the input signals based on an internal reference voltage outputted from the unit gain buffer, external electrostatic discharge protectors connected to a transmission path of the reference voltage and transmission paths of input signals, and internal electrostatic discharge protectors connected to the transmission path of the reference voltage and the transmission paths of the input signals.

Abstract translation: 半导体器件包括用于接收参考电压的焊盘和来自外部设备的输入信号，用于接收参考电压作为输入的单位增益缓冲器，用于基于输出的内部参考电压来识别相应的一个输入信号的输入缓冲器 从单位增益缓冲器，连接到参考电压的传输路径的外部静电放电保护器和输入信号的传输路径，以及连接到参考电压的传输路径和输入信号的传输路径的内部静电放电保护器。

公开(公告)号：US20120275244A1

公开(公告)日：2012-11-01

申请号：US13313370

申请日：2011-12-07

Applicant: Chang-Ho DO

Inventor： Chang-Ho DO

IPC: G11C17/16 ,  G11C7/00

CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/785

Abstract: A semiconductor integrated circuit includes: a fuse; a first driving unit configured to drive a sensing node in response to a first fuse sensing signal; a second driving unit configured to drive the sensing node in response to a second fuse sensing signal, wherein the second driving unit and the fuse form a driving path; a bypass resistor unit connected in parallel with the fuse; and a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.

Abstract translation: 半导体集成电路包括：保险丝; 第一驱动单元，被配置为响应于第一熔丝感测信号驱动感测节点; 第二驱动单元，被配置为响应于第二熔丝感测信号驱动感测节点，其中第二驱动单元和熔丝形成驱动路径; 与保险丝并联连接的旁路电阻器单元; 以及感测单元，被配置为响应于所述感测节点的电压感测所述保险丝的编程状态。

公开(公告)号：US20110032010A1

公开(公告)日：2011-02-10

申请号：US12904763

申请日：2010-10-14

Applicant: Chang-Ho DO

Inventor： Chang-Ho DO

IPC: H03L9/00

CPC classification number: H03K17/223

Abstract: A power up signal generation circuit transits a power up signal at a predetermined target voltage level by providing a predetermined hysteresis characteristic to the target voltage level of a power supply voltage corresponding to the power up signal. The power up signal generation circuit includes a first voltage detection unit that detects a first target voltage level of a power supply voltage to output a detection signal. The circuit also includes a second voltage detection unit that detects a second target voltage level of the power supply voltage in response to a power up signal to output a control signal, wherein the second target voltage level is lower than the first target voltage level. A power up signal drive unit of the circuit activates the power up signal in response to the detection signal and drives the power up signal in response to the control signal.

Abstract translation: 上电信号发生电路通过对与上电信号相对应的电源电压的目标电压电平提供预定的滞后特性来以预定的目标电压电平来转换上电信号。 上电信号发生电路包括：第一电压检测单元，其检测电源电压的第一目标电压电平以输出检测信号。 电路还包括第二电压检测单元，其响应于上电信号检测电源电压的第二目标电压电平，以输出控制信号，其中第二目标电压电平低于第一目标电压电平。 电路的上电信号驱动单元响应于检测信号激活上电信号，并根据控制信号驱动上电信号。

公开(公告)号：US20100207663A1

公开(公告)日：2010-08-19

申请号：US12766616

申请日：2010-04-23

Applicant: Chang-Ho DO

Inventor： Chang-Ho DO

IPC: H03K5/22

CPC classification number: H03K5/1252 ,  H03K5/003 ,  H03K5/08 ,  H04L25/085

Abstract: A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.

Abstract translation: 一种半导体器件，包括：参考电压生成单元，被配置为通过分压正时钟端子和负时钟端子之间的电压差来产生参考电压;以及逻辑判定单元，被配置为基于所述参考值来确定外部信号的逻辑电平 电压。

公开(公告)号：US20090303650A1

公开(公告)日：2009-12-10

申请号：US12345649

申请日：2008-12-29

Applicant: Chang-Ho DO ,  Jae-Hyuk Im

Inventor： Chang-Ho DO ,  Jae-Hyuk Im

IPC: H02H3/08

CPC classification number: G11C29/027 ,  G11C17/165 ,  G11C17/18 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50008

Abstract: Provided is a technology for monitoring the electrical resistance of an element such as a fuse whose resistance is changed due to the electrical stress among internal circuits included in a semiconductor device. The present invention provides a monitoring circuit to monitor the change in the device specification during the device is being programmed and after the device is programmed. The present invention enables the verification of an optimized condition to let the device have a certain electrical resistance, by comparing the load voltage and the fuse voltage with the reference voltage that can sense the range of resistance variation more precisely. Also, it can guarantee device reliability since it is still possible to sense electrical resistance after the electrical stress is being given. Also, the present invention can increase the utility of the fuse by possessing an output to monitor electrical resistance sensed inside of the semiconductor.

Abstract translation: 提供了一种用于监视诸如由于包含在半导体器件中的内部电路之间的电应力而导致电阻改变的熔丝的元件的电阻的技术。 本发明提供了一种监视电路，用于在设备被编程期间以及在设备被编程之后监视设备规格的变化。 本发明能够通过将负载电压和熔丝电压与可以更精确地感测电阻变化范围的参考电压进行比较来验证优化条件以使器件具有一定的电阻。 此外，它可以保证器件的可靠性，因为仍然可以在给出电应力之后感测电阻。 此外，本发明还可以通过具有输出来监测半导体内部感测的电阻来增加熔断器的效用。