公开(公告)号：US08549507B2

公开(公告)日：2013-10-01

申请号：US11843357

申请日：2007-08-22

申请人： Hee Seok Kim ,  Hong-Seok Kim ,  Chang-Woo Baek ,  Jeongwook Kim

发明人： Hee Seok Kim ,  Hong-Seok Kim ,  Chang-Woo Baek ,  Jeongwook Kim

IPC分类号： G06F9/45

CPC分类号： G06F8/4441

摘要： A loop coalescing method and a loop coalescing device are disclosed. The loop coalescing method comprises removing an inner-most loop from among nested loops, so that an outer operation provided outside of the inner-most loop is performed when a condition of a conditional statement is satisfied, generating a guard code by applying an if-conversion method to the conditional statement, and converting a guard by using an instruction calculating the guard of the guard code, the instruction calculating the guard using a register where information related to a period of time corresponding to the number of iterations of the inner-most loop is stored.

摘要翻译： 公开了一种环路聚结方法和回路聚结装置。 循环合并方法包括从嵌套循环中去除最内循环，使得当满足条件语句的条件时，执行在最内循环之外提供的外部操作，通过应用if- 转换方法到条件语句，并且通过使用计算保护码的保护的指令来转换保护，所述指令使用寄存器计算所述保护器，所述寄存器的信息与对应于最内层次的迭代次数相关的时间段 循环被存储。

公开(公告)号：US07774581B2

公开(公告)日：2010-08-10

申请号：US11838511

申请日：2007-08-14

申请人： Chang-Woo Baek ,  Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim

发明人： Chang-Woo Baek ,  Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim

IPC分类号： G06F9/30

CPC分类号： G06F9/3822 ,  G06F9/30156 ,  G06F9/3885

摘要： An apparatus and a method are provided for a parallel processing very long instruction word (VLIW) computer. The apparatus includes: an index code generation unit sequentially generating an index code, which is associated with a number of no operation (NOP) instruction word between effective instruction words, with respect to each of instruction word groups to be executed in a VLIW computer; an instruction compression unit sequentially deleting the NOP instruction word which corresponds to the index code with respect to each of instruction word groups; and an instruction word conversion unit converting the effective instruction words to include the index code, the effective instruction words corresponding to the NOP instruction words.

摘要翻译： 为并行处理非常长的指令字（VLIW）计算机提供了一种装置和方法。 该装置包括：索引代码生成单元，相对于要在VLIW计算机中执行的每个指令字组，顺序生成与有效指令字之间的无操作数（NOP）指令字数相关联的索引码; 指令压缩单元相对于每个指令字组顺序地删除对应于索引代码的NOP指令字; 以及指令字转换单元，将有效指令字转换为包括索引代码，与NOP指令字对应的有效指令字。

公开(公告)号：US08443174B2

公开(公告)日：2013-05-14

申请号：US11838488

申请日：2007-08-14

申请人： Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Suk Jin Kim

发明人： Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Suk Jin Kim

IPC分类号： G06F9/30 ,  G06F9/312

CPC分类号： G06F9/3842

摘要： Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor.

摘要翻译： 提供了一种执行处理器的推测性加载指令的处理器和方法，其中仅在加载指令基本访问存储器的情况下执行加载指令。 在除了上述情况之外的其他情况下执行用于取消操作的加载指令，使得仅在执行推测性加载指令时访问输入/输出（I / O）映射存储区等而出现的问题可以仅被使用 一种类似软件的方法，从而提高处理器的性能。

公开(公告)号：US20080209188A1

公开(公告)日：2008-08-28

申请号：US11838488

申请日：2007-08-14

申请人： Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Suk Jin Kim

发明人： Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Suk Jin Kim

IPC分类号： G06F9/38

CPC分类号： G06F9/3842

摘要： Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor.

摘要翻译： 提供了一种执行处理器的推测性加载指令的处理器和方法，其中仅在加载指令基本访问存储器的情况下执行加载指令。 在除了上述情况之外的其他情况下执行用于取消操作的加载指令，使得仅在执行推测性加载指令时访问输入/输出（I / O）映射存储区等而出现的问题可以仅被使用 一种类似软件的方法，从而提高处理器的性能。

公开(公告)号：US07779225B2

公开(公告)日：2010-08-17

申请号：US11828440

申请日：2007-07-26

申请人： Jong Myon Kim ,  Soojung Ryu ,  Dong-Hoon Yoo ,  Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Kyoung June Min

发明人： Jong Myon Kim ,  Soojung Ryu ,  Dong-Hoon Yoo ,  Hong-Seok Kim ,  Hee Seok Kim ,  Jeongwook Kim ,  Kyoung June Min

IPC分类号： G06F12/00

CPC分类号： G06F8/443 ,  G06F8/447 ,  G06F12/0207

摘要： A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining an a×b×c number of addresses of the memory accessed by the triple loop using the starting address and a function.

摘要翻译： 存储器访问方法包括：从程序中用于访问具有三重循环的存储器的程序代码获取a，b和c，所述三循环的最内循环变量可以具有多个值，b 是三重循环的中间循环变量可能具有的多个值，c是三重循环的最外圈循环变量可能具有的值的数量; 获取由三重循环访问的存储器的起始地址; 并使用起始地址和功能获得由三重回路访问的存储器的a×b×c个地址。

公开(公告)号：US20080120493A1

公开(公告)日：2008-05-22

申请号：US11730170

申请日：2007-03-29

申请人： Dong-Hoon Yoo ,  Soo Jung Ryu ,  Jeong-Wook Kim ,  Hong-Seok Kim ,  Hee Seok Kim

发明人： Dong-Hoon Yoo ,  Soo Jung Ryu ,  Jeong-Wook Kim ,  Hong-Seok Kim ,  Hee Seok Kim

IPC分类号： G06F7/38

CPC分类号： G06F8/443 ,  G06F17/5045 ,  G06F2217/68

摘要： A profiler which provides information to optimize an application specific architecture processor and a program for the processor is provided. The profiler includes: an architecture analyzer which analyzes an architecture description, and generates architecture analysis information, the architecture description describing an architecture of an application specific architecture processor which comprises a plurality of processing elements; a static analyzer which analyzes program static information that describes static information of a program, and generates static analysis information; a dynamic analyzer which analyzes program dynamic information that describes dynamic information of the program, and generates dynamic analysis information, the dynamic information of the program being generated by simulating the program; and a cross profiling analyzer which generates information for optimizing the application specific architecture processor to implement the program based on at least one of the architecture analysis information, the static analysis information, and the dynamic analysis information.

摘要翻译： 提供了一种提供信息以优化特定于应用的架构处理器和用于处理器的程序的分析器。 分析器包括：架构分析器，其分析架构描述并生成架构分析信息，描述包括多个处理元件的应用特定架构处理器的架构的架构描述; 静态分析器，分析程序静态信息，描述程序的静态信息，并生成静态分析信息; 动态分析器，其分析描述所述程序的动态信息的程序动态信息，并且生成动态分析信息，所述程序的动态信息是通过模拟所述程序而产生的; 以及交叉分析分析器，其基于所述架构分析信息，所述静态分析信息和所述动态分析信息中的至少一个，生成用于优化所述应用专用架构处理器以实现所述程序的信息。

公开(公告)号：US08490066B2

公开(公告)日：2013-07-16

申请号：US11730170

申请日：2007-03-29

申请人： Dong-Hoon Yoo ,  Soo-Jung Ryu ,  Jeong-Wook Kim ,  Hong-Seok Kim ,  Hee Seok Kim

发明人： Dong-Hoon Yoo ,  Soo-Jung Ryu ,  Jeong-Wook Kim ,  Hong-Seok Kim ,  Hee Seok Kim

IPC分类号： G06F15/76 ,  G06F9/44

CPC分类号： G06F8/443 ,  G06F17/5045 ,  G06F2217/68

摘要： A profiler which provides information to optimize an application specific architecture processor and a program for the processor is provided. The profiler includes: an architecture analyzer which analyzes an architecture description, and generates architecture analysis information, the architecture description describing an architecture of an application specific architecture processor which comprises a plurality of processing elements; a static analyzer which analyzes program static information that describes static information of a program, and generates static analysis information; a dynamic analyzer which analyzes program dynamic information that describes dynamic information of the program, and generates dynamic analysis information, the dynamic information of the program being generated by simulating the program; and a cross profiling analyzer which generates information for optimizing the application specific architecture processor to implement the program based on at least one of the architecture analysis information, the static analysis information, and the dynamic analysis information.

摘要翻译： 提供了一种提供信息以优化特定于应用的架构处理器和用于处理器的程序的分析器。 分析器包括：架构分析器，其分析架构描述并生成架构分析信息，描述包括多个处理元件的应用特定架构处理器的架构的架构描述; 静态分析器，分析程序静态信息，描述程序的静态信息，并生成静态分析信息; 动态分析器，其分析描述所述程序的动态信息的程序动态信息，并且生成动态分析信息，所述程序的动态信息是通过模拟所述程序而产生的; 以及交叉分析分析器，其基于所述架构分析信息，所述静态分析信息和所述动态分析信息中的至少一个，生成用于优化所述应用专用架构处理器以实现所述程序的信息。

公开(公告)号：US09152418B2

公开(公告)日：2015-10-06

申请号：US11487407

申请日：2006-07-17

申请人： Hee Seok Kim ,  Dong-Hoon Yoo ,  Jeong Wook Kim ,  Soo Jung Ryu

发明人： Hee Seok Kim ,  Dong-Hoon Yoo ,  Jeong Wook Kim ,  Soo Jung Ryu

IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3012 ,  G06F9/30105 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3863

摘要： A processor including a coarse grained array including a plurality of processing elements, a central register file including a first plurality of register files, a shadow central register file including a second plurality of register files, each of the second plurality of register files corresponding to each of the first plurality of register files included in the central register file, and a plurality of shadow register files, each of the plurality of shadow register files corresponding to each of a third plurality of register files included in predetermined processing elements selected from the plurality of processing elements.

摘要翻译： 一种处理器，包括包括多个处理元件的粗粒子阵列，包括第一多个寄存器文件的中央寄存器文件，包括第二多个寄存器文件的影子中心寄存器文件，与每个寄存器文件相对应的第二多个寄存器堆中的每一个 包括在中央寄存器文件中的第一多个寄存器文件和多个影子寄存器文件，多个影子寄存器文件中的每一个对应于包括在从多个寄存器文件中选择的预定处理元件中的第三多个寄存器文件中的每一个 处理元件。

公开(公告)号：US08788158B2

公开(公告)日：2014-07-22

申请号：US13492201

申请日：2012-06-08

申请人： Hee Seok Kim

发明人： Hee Seok Kim

IPC分类号： B60K17/06 ,  B60K17/12 ,  F16H59/08 ,  F16H61/32 ,  F16H59/10 ,  F16H59/12

CPC分类号： F16H59/08 ,  F16H59/105 ,  F16H59/12 ,  F16H2059/081 ,  F16H2061/326 ,  Y10T74/2003

摘要： A shifting device for a vehicle and a shifting system using the same are provided. The shifting device for a vehicle may be connected to a transmission of the vehicle via a cable to operate the transmission. More specifically, the shifting device may include an interface module which receives an input of a shift signal, and an actuator which is connected to one end of the cable, and operates the cable according to the shift signal inputted to the interface module to operate the transmission connected to the other end of the cable.

摘要翻译： 提供了一种用于车辆的换档装置和使用其的变速系统。 用于车辆的换档装置可以经由电缆连接到车辆的变速器以操作变速器。 更具体地，换档装置可以包括接收换挡信号的输入的接口模块和连接到电缆的一端的致动器，并且根据输入到接口模块的移位信号来操作电缆，以操作 传输连接到电缆的另一端。

公开(公告)号：US08154547B2

公开(公告)日：2012-04-10

申请号：US13090924

申请日：2011-04-20

申请人： Kyoung June Min ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

发明人： Kyoung June Min ,  Jong Myon Kim ,  Hee Seok Kim ,  Jeong Wook Kim ,  Suk Jin Kim

IPC分类号： G06T15/40

CPC分类号： G06T15/405

摘要： A method and system for an early Z test in a tile-based three-dimensional rendering is provided. In the method and system for an early Z test, a portion which is not displayed to a user is removed prior to performing a rasterization process, and thereby performing the 3D rendering efficiently. The method includes segmenting a scene into tiles for performing a rendering with respect to a triangle; selecting a first tile of the tiles, which has a tile Z value less than a minimum Z value of the triangle; and performing the rendering with respect to the triangle in remaining tiles excluding the selected first tile of the tiles.

摘要翻译： 提供了一种基于瓦片的三维渲染的早期Z检验的方法和系统。 在早期Z测试的方法和系统中，在执行光栅化处理之前去除了不向用户显示的部分，从而有效地执行3D渲染。 该方法包括将场景分割成用于执行相对于三角形的呈现的图块; 选择瓦片的第一瓦片，其具有小于所述三角形的最小Z值的瓦片Z值; 以及在除了所选择的瓦片的所选择的第一瓦片之外的剩余瓦片中执行相对于三角形的呈现。