摘要:
Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor.
摘要:
Provided is a processor and method of performing speculative load instructions of the processor in which a load instruction is performed only in the case where the load instruction substantially accesses a memory. A load instruction for canceling operations is performed in other cases except the above case, so that problems occurring by accessing an input/output (I/O) mapped memory area and the like at the time of performing speculative load instructions can be prevented using only a software-like method, thereby improving the performance of a processor.
摘要:
A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining an a×b×c number of addresses of the memory accessed by the triple loop using the starting address and a function.
摘要:
A loop coalescing method and a loop coalescing device are disclosed. The loop coalescing method comprises removing an inner-most loop from among nested loops, so that an outer operation provided outside of the inner-most loop is performed when a condition of a conditional statement is satisfied, generating a guard code by applying an if-conversion method to the conditional statement, and converting a guard by using an instruction calculating the guard of the guard code, the instruction calculating the guard using a register where information related to a period of time corresponding to the number of iterations of the inner-most loop is stored.
摘要:
An apparatus and a method are provided for a parallel processing very long instruction word (VLIW) computer. The apparatus includes: an index code generation unit sequentially generating an index code, which is associated with a number of no operation (NOP) instruction word between effective instruction words, with respect to each of instruction word groups to be executed in a VLIW computer; an instruction compression unit sequentially deleting the NOP instruction word which corresponds to the index code with respect to each of instruction word groups; and an instruction word conversion unit converting the effective instruction words to include the index code, the effective instruction words corresponding to the NOP instruction words.
摘要:
A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core.
摘要:
A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core.
摘要:
A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.
摘要:
A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.
摘要:
Provided are a glass powder represented as aLi2O-bK2O-cBaO-dB2O3-eSiO2wherein a+b+c+d+e=1, and 0.01≦a≦0.1, 0.01≦b≦0.1, 0.01≦c≦0.1, 0.05≦d≦0.3, and 0.3≦e≦0.7 are satisfied in terms of mol %, a method of manufacturing the same, and a multi-layered ceramic material using the same. Therefore, a nano glass powder having an average particle size of 100nm or less and uniform particle size distribution can be manufactured using liquid phase deposition, specifically, a sol-gel method. In addition, the glass powder can be used as sintering additives to decrease a sintering temperature by about 100° C. in comparison with conventional glass upon manufacture of a ceramic material such as MLCC and MLCI, which can be sintered at a low temperature, contributing to improvement of dielectric capacity and inductance capacity of the parts and increasing quality coefficient.
摘要翻译:提供一种表示为Li 2 O-bK 2 O-cBaO-dB 2 O 3 -eSiO 2的玻璃粉末,其中a + b + c + d + e = 1,和0.01 @ a @ 0.1,01 @ b @ 0.1,01 @ c @ 0.1,0.05@d 以0.3%,0.3≤e≤0.7,以摩尔%表示,其制造方法和使用其的多层陶瓷材料。 因此,平均粒径为100nm以下且粒径分布均匀的纳米玻璃粉末可以使用液相沉积,特别是溶胶 - 凝胶法制造。 此外,与常规玻璃相比,玻璃粉末可以用作烧结添加剂以将烧结温度降低约100℃,而陶瓷材料如MLCC和MLCI可以在低温下烧结而成 提高零件的介电容量和电感量,提高品质系数。