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    Semiconductor Devices Including Fin Shaped Semiconductor Regions and Stress Inducing Layers
    1.
    发明申请
    Semiconductor Devices Including Fin Shaped Semiconductor Regions and Stress Inducing Layers 有权
    包括鳍状半导体区域和应力诱导层的半导体器件

    公开(公告)号：US20110272738A1

    公开(公告)日：2011-11-10

    申请号：US13096324

    申请日：2011-04-28

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-won Kim ,  Sung-dae Suk

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-won Kim ,  Sung-dae Suk

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

    摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

    SEMICONDUCTOR DEVICES INCLUDING FIN SHAPED SEMICONDUCTOR REGIONS AND STRESS INDUCING LAYERS
    2.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING FIN SHAPED SEMICONDUCTOR REGIONS AND STRESS INDUCING LAYERS 有权
    半导体器件，其中包括金属半导体半导体区域和应力诱导层

    公开(公告)号：US20110079859A1

    公开(公告)日：2011-04-07

    申请号：US12950064

    申请日：2010-11-19

    申请人： Chang-Woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    发明人： Chang-Woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

    摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

    Semiconductor devices including fin shaped semiconductor regions and stress inducing layers
    3.
    发明授权
    Semiconductor devices including fin shaped semiconductor regions and stress inducing layers 有权
    包括鳍状半导体区域和应力诱导层的半导体器件

    公开(公告)号：US08461653B2

    公开(公告)日：2013-06-11

    申请号：US13096324

    申请日：2011-04-28

    申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    IPC分类号： H01L29/41

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

    摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

    Semiconductor devices including fin shaped semiconductor regions and stress inducing layers
    4.
    发明授权
    Semiconductor devices including fin shaped semiconductor regions and stress inducing layers 有权
    包括鳍状半导体区域和应力诱导层的半导体器件

    公开(公告)号：US07952151B2

    公开(公告)日：2011-05-31

    申请号：US12950064

    申请日：2010-11-19

    申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    IPC分类号： H01L29/41

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

    摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

    Semiconductor devices including stress inducing layers
    5.
    发明申请
    Semiconductor devices including stress inducing layers 有权
    包括应力诱导层的半导体器件

    公开(公告)号：US20060022268A1

    公开(公告)日：2006-02-02

    申请号：US11190254

    申请日：2005-07-26

    申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A semiconductor device may include a substrate and a fin shaped semiconductor region on the substrate. The fin shaped semiconductor region may include a channel region and first and second junction regions on opposite sides of the channel region. A gate electrode may be provided on the channel region of the fin shaped semiconductor region, and a stress inducing layer on the fin shaped semiconductor region.

    摘要翻译： 半导体器件可以包括衬底和衬底上的鳍状半导体区域。 鳍状半导体区域可以包括沟道区域和在沟道区域的相对侧上的第一和第二结区域。 可以在鳍状半导体区域的沟道区域上设置栅电极，在鳍状半导体区域上设置应力感应层。

    Semiconductor devices including channel and junction regions of different semiconductor materials
    6.
    发明授权
    Semiconductor devices including channel and junction regions of different semiconductor materials 有权
    半导体器件包括不同半导体材料的沟道和结区

    公开(公告)号：US07859064B1

    公开(公告)日：2010-12-28

    申请号：US11849577

    申请日：2007-09-04

    申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    IPC分类号： H01L29/41

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

    摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

    Semiconductor devices including stress inducing layers
    7.
    发明授权
    Semiconductor devices including stress inducing layers 有权
    包括应力诱导层的半导体器件

    公开(公告)号：US07271456B2

    公开(公告)日：2007-09-18

    申请号：US11190254

    申请日：2005-07-26

    申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

    IPC分类号： H01L29/41

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A semiconductor device may include a substrate and a fin shaped semiconductor region on the substrate. The fin shaped semiconductor region may include a channel region and first and second junction regions on opposite sides of the channel region. A gate electrode may be provided on the channel region of the fin shaped semiconductor region, and a stress inducing layer on the fin shaped semiconductor region.

    摘要翻译： 半导体器件可以包括衬底和衬底上的鳍状半导体区域。 鳍状半导体区域可以包括沟道区域和在沟道区域的相对侧上的第一和第二结区域。 可以在鳍状半导体区域的沟道区域上设置栅电极，在鳍状半导体区域上设置应力感应层。

    Method of fabricating a semiconductor device with multiple channels
    8.
    发明授权
    Method of fabricating a semiconductor device with multiple channels 有权
    制造具有多个通道的半导体器件的方法

    公开(公告)号：US08008141B2

    公开(公告)日：2011-08-30

    申请号：US12503594

    申请日：2009-07-15

    申请人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

    发明人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

    IPC分类号： H01L21/8232

    CPC分类号： H01L29/78696 ,  H01L29/1083 ,  H01L29/66787

    摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

    摘要翻译： 具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并具有彼此相对的侧壁的一对导电区域。 在导电区域之间的半导体衬底上设置有部分绝缘层。 至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接 到第一个方向。 栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

    SEMICONDUCTOR DEVICE WITH MULTIPLE CHANNELS AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE WITH MULTIPLE CHANNELS AND METHOD OF FABRICATING THE SAME 有权
    具有多个通道的半导体器件及其制造方法

    公开(公告)号：US20090275177A1

    公开(公告)日：2009-11-05

    申请号：US12503594

    申请日：2009-07-15

    申请人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

    发明人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78696 ,  H01L29/1083 ,  H01L29/66787

    摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

    摘要翻译： 具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并且具有彼此面对的侧壁的一对导电区域。 在导电区域之间的半导体衬底上设置有部分绝缘层。 至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接 到第一个方向。 栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

    Method of fabricating a MOS field effect transistor having plurality of channels
    10.
    发明授权
    Method of fabricating a MOS field effect transistor having plurality of channels 有权
    制造具有多个通道的MOS场效应晶体管的方法

    公开(公告)号：US07588977B2

    公开(公告)日：2009-09-15

    申请号：US11452066

    申请日：2006-06-13

    申请人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

    发明人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

    IPC分类号： H01L29/768

    CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/7831

    摘要： A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

    摘要翻译： 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法，在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案，并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案，并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案，形成第一开口。 然后，蚀刻填充材料层以形成第二开口，去除暴露的第一材料层以暴露半导体层，并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。