公开(公告)号：US20090275177A1

公开(公告)日：2009-11-05

申请号：US12503594

申请日：2009-07-15

申请人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

发明人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/1083 ,  H01L29/66787

摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

摘要翻译： 具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并且具有彼此面对的侧壁的一对导电区域。 在导电区域之间的半导体衬底上设置有部分绝缘层。 至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接 到第一个方向。 栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

公开(公告)号：US08008141B2

公开(公告)日：2011-08-30

申请号：US12503594

申请日：2009-07-15

申请人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

发明人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

IPC分类号： H01L21/8232

CPC分类号： H01L29/78696 ,  H01L29/1083 ,  H01L29/66787

摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

摘要翻译： 具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并具有彼此相对的侧壁的一对导电区域。 在导电区域之间的半导体衬底上设置有部分绝缘层。 至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接 到第一个方向。 栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

公开(公告)号：US07579657B2

公开(公告)日：2009-08-25

申请号：US11517211

申请日：2006-09-07

申请人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

发明人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

IPC分类号： H01L29/786

CPC分类号： H01L29/78696 ,  H01L29/1083 ,  H01L29/66787

摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

摘要翻译： 具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并且具有彼此面对的侧壁的一对导电区域。 在导电区域之间的半导体衬底上设置有部分绝缘层。 至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接 到第一个方向。 栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

公开(公告)号：US20070158679A1

公开(公告)日：2007-07-12

申请号：US11517211

申请日：2006-09-07

申请人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

发明人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

IPC分类号： H01L29/74

CPC分类号： H01L29/78696 ,  H01L29/1083 ,  H01L29/66787

摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

摘要翻译： 具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并具有彼此相对的侧壁的一对导电区域。 在导电区域之间的半导体衬底上设置有部分绝缘层。 至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接 到第一个方向。 栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

公开(公告)号：US20050176219A1

公开(公告)日：2005-08-11

申请号：US11050557

申请日：2005-02-03

申请人： Min-sang Kim ,  Chang-woo Oh ,  Dong-won Kim ,  Kyoung-hwan Yeo ,  Sung-min Kim

发明人： Min-sang Kim ,  Chang-woo Oh ,  Dong-won Kim ,  Kyoung-hwan Yeo ,  Sung-min Kim

IPC分类号： H01L21/336 ,  C30B1/00 ,  H01L29/06

CPC分类号： H01L29/0653 ,  H01L29/0649 ,  H01L29/6659

摘要： A Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) can be formed by growing an epitaxial semiconductor layer on an upper surface of a sacrificial crystalline structure and on a substrate to form a buried sacrificial structure. The buried sacrificial structure can be removed to form a void in place of the buried sacrificial structure and a device isolation layer can be formed in the void.

摘要翻译： 可以通过在牺牲晶体结构的上表面上和衬底上生长外延半导体层以形成掩埋牺牲结构来形成金属氧化物半导体场效应晶体管（MOSFET）。 可以去除掩埋的牺牲结构以形成空穴而不是埋入的牺牲结构，并且可以在空隙中形成器件隔离层。

公开(公告)号：US07605025B2

公开(公告)日：2009-10-20

申请号：US11050557

申请日：2005-02-03

申请人： Min-sang Kim ,  Chang-woo Oh ,  Dong-won Kim ,  Kyoung-hwan Yeo ,  Sung-min Kim

发明人： Min-sang Kim ,  Chang-woo Oh ,  Dong-won Kim ,  Kyoung-hwan Yeo ,  Sung-min Kim

IPC分类号： H01L21/00 ,  H01L21/76

CPC分类号： H01L29/0653 ,  H01L29/0649 ,  H01L29/6659

摘要： A Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) can be formed by growing an epitaxial semiconductor layer on an upper surface of a sacrificial crystalline structure and on a substrate to form a buried sacrificial structure. The buried sacrificial structure can be removed to form a void in place of the buried sacrificial structure and a device isolation layer can be formed in the void.

摘要翻译： 可以通过在牺牲晶体结构的上表面上和衬底上生长外延半导体层以形成掩埋牺牲结构来形成金属氧化物半导体场效应晶体管（MOSFET）。 可以去除掩埋的牺牲结构以形成空穴而不是埋入的牺牲结构，并且可以在空隙中形成器件隔离层。

公开(公告)号：US07588977B2

公开(公告)日：2009-09-15

申请号：US11452066

申请日：2006-06-13

申请人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

发明人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

IPC分类号： H01L29/768

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/7831

摘要： A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

摘要翻译： 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法，在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案，并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案，并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案，形成第一开口。 然后，蚀刻填充材料层以形成第二开口，去除暴露的第一材料层以暴露半导体层，并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。

公开(公告)号：US20090294864A1

公开(公告)日：2009-12-03

申请号：US12538222

申请日：2009-08-10

申请人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

发明人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/7831

摘要： A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

摘要翻译： 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法，在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案，并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案，并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案，形成第一开口。 然后，蚀刻填充材料层以形成第二开口，去除暴露的第一材料层以暴露半导体层，并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。

公开(公告)号：US20070004124A1

公开(公告)日：2007-01-04

申请号：US11452066

申请日：2006-06-13

申请人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

发明人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

IPC分类号： H01L21/8244

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/7831

摘要： A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

摘要翻译： 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法，在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案，并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案，并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案，形成第一开口。 然后，蚀刻填充材料层以形成第二开口，去除暴露的第一材料层以暴露半导体层，并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。

公开(公告)号：US07795687B2

公开(公告)日：2010-09-14

申请号：US12538222

申请日：2009-08-10

申请人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

发明人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/7831

摘要： A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

摘要翻译： 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法，在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案，并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案，并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案，形成第一开口。 然后，蚀刻填充材料层以形成第二开口，去除暴露的第一材料层以暴露半导体层，并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。