公开(公告)号：US20140042520A1

公开(公告)日：2014-02-13

申请号：US14057380

申请日：2013-10-18

申请人： Changhyun Lee ,  Byoungkeun Son ,  Hyejin Cho

发明人： Changhyun Lee ,  Byoungkeun Son ,  Hyejin Cho

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7926

摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

摘要翻译： 三维（3D）非易失性存储器件包括其中具有第二导电类型（例如，P型）的阱区和在该区域上具有第一导电类型（例如，N型）的公共源极区的衬底。 凹部部分（或完全）延伸穿过公共源区域。 衬底上的垂直堆叠的非易失性存储器单元包括间隔开的栅电极的垂直堆叠和垂直有源区，该垂直有源区延伸在间隔开的栅电极的垂直堆叠的侧壁上并在凹槽的侧壁上延伸。 栅极电介质层在相互间隔开的栅电极的垂直叠层和垂直有源区之间延伸。 栅极电介质层可以包括隧道绝缘层，电荷存储层，相对高的带隙势垒介电层和具有相对高的介电强度的阻挡绝缘层的复合材料。

公开(公告)号：US08569827B2

公开(公告)日：2013-10-29

申请号：US13220376

申请日：2011-08-29

申请人： Changhyun Lee ,  Byoungkeun Son ,  Hyejin Cho

发明人： Changhyun Lee ,  Byoungkeun Son ,  Hyejin Cho

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7926

摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess is provided, which extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells are provided on the substrate. This vertical stack of nonvolatile memory cells includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers are provided, which extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

摘要翻译： 三维（3D）非易失性存储器件包括其中具有第二导电类型（例如，P型）的阱区和在该区域上具有第一导电类型（例如N型）的公共源极区的衬底。 设置有通过共同源极区域部分（或完全）延伸的凹部。 在基板上提供了一堆非易失性存储单元。 这种垂直堆叠的非易失性存储单元包括间隔开的栅电极的垂直叠层和垂直有源区，该垂直有源区延伸在间隔开的栅电极的垂直叠层的侧壁上并在凹槽的侧壁上延伸。 提供栅介电层，其在相互间隔开的栅电极的垂直叠层和垂直有源区之间延伸。 栅极电介质层可以包括隧道绝缘层，电荷存储层，相对高的带隙势垒介电层和具有相对高的介电强度的阻挡绝缘层的复合材料。