公开(公告)号：US12080340B2

公开(公告)日：2024-09-03

申请号：US17737109

申请日：2022-05-05

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Sungsoo Chi ,  Shuyan Jin ,  Fengqin Zhang

IPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C11/4094

CPC分类号： G11C11/4096 ,  G11C11/4091 ,  G11C11/4094

摘要： A control circuit, a method for reading and writing and a memory are provided. The control circuit includes a pre-charge circuit, an amplification circuit and an equalization circuit. The pre-charge circuit is directly electrically connected to at least one of a bit line or a complementary bit line. The amplification circuit has a first node and a second node. The equalization circuit is connected between the first node and the bit line and between the second node and the complementary bit line.

公开(公告)号：US20230143797A1

公开(公告)日：2023-05-11

申请号：US18153420

申请日：2023-01-12

申请人： Changxin Memory Technologies, Inc.

发明人： Sungsoo Chi ,  Fengqin Zhang ,  Shuyan Jin

IPC分类号： G11C8/08 ,  G11C8/14

CPC分类号： G11C8/08 ,  G11C8/14

摘要： Embodiments of the present disclosure provide a word line driver, a word line driver array, and a semiconductor structure, relating to the technical field of semiconductors. The word line driver includes: a zeroth P-channel metal oxide semiconductor (PMOS) transistor, a zeroth N-channel metal oxide semiconductor (NMOS) transistor, and a first NMOS transistor, the zeroth PMOS transistor being provided with a gate connected to a gate of the first NMOS transistor and configured to receive a first control signal, a source configured to receive a second control signal, and a drain connected to a drain of the first NMOS transistor, the zeroth NMOS transistor being provided with a gate configured to receive a second control complementary signal, and a drain of the zeroth NMOS transistor and the drain of the first NMOS transistor being configured to be connected to a word line.

公开(公告)号：US12027201B2

公开(公告)日：2024-07-02

申请号：US17743497

申请日：2022-05-13

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Sungsoo Chi ,  Jia Wang ,  Ying Wang ,  Shuyan Jin ,  Fengqin Zhang

IPC分类号： G11C11/4094 ,  G11C11/4091

CPC分类号： G11C11/4094 ,  G11C11/4091

摘要： A column select signal cell circuit, a bit line sense circuit and a memory are disclosed. The column select signal cell circuit includes four column select cells, each of which includes 4*N input and output ports, 4*N bit line connection ports and one control port. The control ports of a first column select cell and a fourth column select cell are connected to a first column select signal, and the control ports of a second column select cell and a third column select cell are connected to a second column select signal. The bit line connection ports of the first column select cell and the third column select cell are connected to 8*N bit lines of a first storage unit group, the bit line connection ports of the second column select cell and the fourth column select cell are connected to 8*N bit lines of a second storage unit group.

公开(公告)号：US12119047B2

公开(公告)日：2024-10-15

申请号：US17847825

申请日：2022-06-23

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Sungsoo Chi ,  Shuyan Jin ,  Fengqin Zhang

IPC分类号： G11C7/02 ,  G11C11/4091

CPC分类号： G11C11/4091

摘要： A readout circuit structure is provided, which includes: a first sense amplification circuit and a second sense amplification circuit, disposed adjacent to each other along an extension direction of a bit line, here the first sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a first bit line, and is coupled to the other memory array by a first complementary bit line, and the second sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a second bit line, and is coupled to the other memory array by a second complementary bit line; a first equalization pipe, connected to the first bit line; a second equalization pipe, connected to the first complementary bit line; a third equalization pipe, connected to the second bit line; and a fourth equalization pipe, connected to the second complementary bit line.

公开(公告)号：US11862239B2

公开(公告)日：2024-01-02

申请号：US17476583

申请日：2021-09-16

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Sungsoo Chi ,  Jia Wang ,  Ying Wang ,  Shuyan Jin ,  Fengqin Zhang

IPC分类号： G11C7/10 ,  G11C11/4097 ,  G06F11/10 ,  G11C11/4091

CPC分类号： G11C11/4097 ,  G06F11/1068 ,  G11C11/4091

摘要： A bit line sense circuit and a memory are disclosed in the present application. The bit line sense circuit includes: L storage unit groups, each storage unit group including H bit lines, both L and H being positive integers greater than or equal to 2; and M sense amplifier groups, configured to write or read storage data to or from the bit lines in the storage unit groups and electrically connected to the L storage unit groups, M being an integer multiple of L or L being an integer multiple of M. Two adjacent bit lines of the H bit lines are connected to the different sense amplifier groups.

公开(公告)号：US20230005522A1

公开(公告)日：2023-01-05

申请号：US17847825

申请日：2022-06-23

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： SUNGSOO CHI ,  Shuyan Jin ,  Fengqin Zhang

IPC分类号： G11C11/4091

摘要： A readout circuit structure is provided, which includes: a first sense amplification circuit and a second sense amplification circuit, disposed adjacent to each other along an extension direction of a bit line, here the first sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a first bit line, and is coupled to the other memory array by a first complementary bit line, and the second sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a second bit line, and is coupled to the other memory array by a second complementary bit line; a first equalization pipe, connected to the first bit line; a second equalization pipe, connected to the first complementary bit line; a third equalization pipe, connected to the second bit line; and a fourth equalization pipe, connected to the second complementary bit line.