Live loaded packing for valve
    1.
    发明授权
    Live loaded packing for valve 有权
    活塞式填料

    公开(公告)号:US07219878B1

    公开(公告)日:2007-05-22

    申请号:US11263308

    申请日:2005-10-31

    Inventor: Charles A. Hart

    CPC classification number: F16F1/027

    Abstract: In accordance with the present invention, there is provided a lie loaded packing assembly for a valve which comprises a valve body defining a passage having a valve stem moveably disposed therein and selectively moveable between open and closed positions. Extending about a portion of the valve stem is a packing. One end of a sleeve of the valve bears axially onto and compresses the packing, with a spigot of the valve being cooperatively engaged to the opposite end of the sleeve. A clamp of the valve is cooperatively engaged to the valve body, with a pair of bolts extending between and being secured to the clamp, the spigot, and a flange member which is itself cooperatively engaged to the spigot. The combination of the bolt, spigot and flange member provide an integral spring construction for the valve.

    Abstract translation: 根据本发明,提供了一种用于阀门的负载包装组件,其包括限定具有可动地设置在其中的阀杆的通道的阀体,并且可选择性地在打开和关闭位置之间移动。 延伸大约一部分阀杆是一个包装。 阀的套筒的一端轴向地承载并压缩衬垫,阀的插口协同地接合到套筒的相对端。 阀的夹具与阀体配合地接合,一对螺栓在夹具之间延伸并固定到夹具上,套管以及凸缘部件,凸缘部件本身协作地接合到套管上。 螺栓,套管和凸缘构件的组合为阀提供了一体的弹簧结构。

    Cache contained type semiconductor memory device and operating method
therefor
    3.
    发明授权
    Cache contained type semiconductor memory device and operating method therefor 失效
    高速缓存包含类型的半导体存储器件及其操作方法

    公开(公告)号:US5111386A

    公开(公告)日:1992-05-05

    申请号:US538605

    申请日:1990-06-14

    CPC classification number: G11C8/12 G06F12/0893

    Abstract: A dynamic random access memory with a fast serial access mode for use in a simple cache system includes a plurality of memory cell blocks prepared by division of a memory cell array, a plurality of data latches each provided for each column in the memory cell blocks and a block selector. When a cache miss signal is produced by the cache system, data on the column in the cell block selected by the block decoder are transferred into the data latches provided for the columns in the selected block after selection. When a cache hit signal is produced by the cache system, the data latches are isolated from the memory cell array. Accessing is made to at least one of the data latches based on an externally applied column address on cache hit, and to at least one of the columns in the selected block based on the column address on cache miss.

    Abstract translation: 具有用于简单高速缓存系统的快速串行访问模式的动态随机存取存储器包括通过对存储单元阵列进行划分而分别制备的多个存储单元块,为存储单元块中的每列提供的多个数据锁存器,以及 块选择器。 当由高速缓存系统产生高速缓存未命中信号时,由块解码器选择的单元块中的列上的数据被传送到在选择之后为选定块中的列提供的数据锁存器中。 当缓存命中信号由高速缓存系统产生时,数据锁存器与存储单元阵列隔离。 基于高速缓存命中的外部应用列地址,以及基于高速缓存未命中的列地址的所选块中的至少一个列,对至少一个数据锁存器进行访问。

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