公开(公告)号：US07917730B2

公开(公告)日：2011-03-29

申请号：US12060683

申请日：2008-04-01

申请人： Charles Francis Marino ,  John Thomas Holloway, Jr. ,  Praveen S. Reddy ,  William John Starke

发明人： Charles Francis Marino ,  John Thomas Holloway, Jr. ,  Praveen S. Reddy ,  William John Starke

IPC分类号： G06F13/40

CPC分类号： G06F15/8007

摘要： A multi-chip processor apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk that communicates information between multiple compute elements situated along the primary interconnect trunk. That multiple processor chip includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of that multiple processor chip. The secondary interconnect trunk intersects the primary interconnect trunk at an intersection at which a bus control element is located. The bus control element includes a primary trunk interface that couples to the primary interconnect trunk at the intersection to enable the bus control element to control on-chip communication among the compute elements via coherency signals on the primary interconnect trunk. The bus control element includes a secondary trunk interface coupled to the secondary interconnect trunk.

摘要翻译： 多芯片处理器装置在基板上包括多个处理器芯片。 多个处理器芯片中的至少一个包括具有主互连干线的管芯，其在沿着主互连干线位于的多个计算元件之间传送信息。 该多处理器芯片包括可相对于主互连干线垂直定向的次级互连干线。 辅助互连中继线通过多处理器芯片周边的多个I / O接口来传送芯片外的信息。 次互连干线在总线控制元件所在的交点处与主互连干线相交。 总线控制元件包括在交叉点处耦合到主互连干线的主干接口，以使得总线控制元件能够通过主互连干线上的相干信号来控制计算元件之间的片上通信。 总线控制元件包括耦合到辅助互连主干的辅助中继接口。

公开(公告)号：US20090248940A1

公开(公告)日：2009-10-01

申请号：US12060683

申请日：2008-04-01

申请人： Charles Francis Marino ,  John Thomas Hollaway, JR. ,  Praveen S. Reddy ,  William John Starke

发明人： Charles Francis Marino ,  John Thomas Hollaway, JR. ,  Praveen S. Reddy ,  William John Starke

IPC分类号： G06F13/14

CPC分类号： G06F15/8007

摘要： An integrated circuit (IC) processor chip apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. That multiple processor chip includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of that multiple processor chip. The I/O interfaces may be distributed uniformly along portions of the perimeter of that multiple processor chip.

摘要翻译： 集成电路（IC）处理器芯片装置在基板上包括多个处理器芯片。 多个处理器芯片中的至少一个包括具有主互连干线的管芯，用于在沿着主互连干线位于的多个计算元件之间进行信息通信。 该多处理器芯片包括可相对于主互连干线垂直定向的次级互连干线。 辅助互连中继线通过多处理器芯片周边的多个I / O接口来传送芯片外的信息。 I / O接口可以沿着该多处理器芯片的周边的一部分均匀地分布。

公开(公告)号：US06606680B2

公开(公告)日：2003-08-12

申请号：US09895224

申请日：2001-06-29

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

IPC分类号： G06F1202

CPC分类号： G06F12/0897 ,  G11C7/22 ,  G11C11/408 ,  G11C2207/104

摘要： An apparatus for accessing a banked embedded dynamic random access memory device is disclosed. The apparatus for accessing a banked embedded dynamic random access memory (DRAM) device comprises a general functional control logic and a bank RAS controller. The general functional control logic is coupled to each bank of the banked embedded DRAM device. Coupled to the general functional control logic, the bank RAS controller includes a rotating shift register having multiple bits. Each bit within the rotating shift register corresponds to each bank of the banked embedded DRAM device. As such, a first value within a bit of the rotating shift register allows accesses to an associated bank of the banked embedded DRAM device, and a second value within a bit of the rotating shift register denies accesses to an associated bank of the banked embedded DRAM device.

摘要翻译： 公开了一种用于访问嵌入式动态随机存取存储器件的装置。 用于访问堆叠式嵌入式动态随机存取存储器（DRAM）装置的装置包括通用功能控制逻辑和银行RAS控制器。 一般的功能控制逻辑耦合到组合的嵌入式DRAM设备的每个组。 耦合到一般功能控制逻辑，银行RAS控制器包括具有多个位的旋转移位寄存器。 旋转移位寄存器内的每个位对应于组合嵌入式DRAM器件的每一组。 这样，旋转移位寄存器的一位内的第一值允许访问分组的嵌入式DRAM设备的相关联的存储体，并且旋转移位寄存器的一位内的第二值拒绝对相关联的组的嵌入式DRAM 设备。

公开(公告)号：US06574719B2

公开(公告)日：2003-06-03

申请号：US09903720

申请日：2001-07-12

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

IPC分类号： G06F1200

CPC分类号： G06F13/28 ,  G06F13/4243

摘要： An apparatus for providing concurrent communications between multiple memory devices and a processor is disclosed. Each of the memory device includes a driver, a phase/cycle adjust sensing circuit, and a bus alignment communication logic. Each phase/cycle adjust sensing circuit detects an occurrence of a cycle adjustment from a corresponding driver within a memory device. If an occurrence of a cycle adjustment has been detected, the bus alignment communication logic communicates the occurrence of a cycle adjustment to the processor. The bus alignment communication logic also communicates the occurrence of a cycle adjustment to the bus alignment communication logic in the other memory devices. There are multiple receivers within the processor, and each of the receivers is designed to receive data from a respective driver in a memory device. Each of the receivers includes a cycle delay block. The receiver that had received the occurrence of a cycle adjustment informs the other receivers that did not receive the occurrence of a cycle adjustment to use their cycle delay block to delay the incoming data for at least one cycle.

摘要翻译： 公开了一种用于在多个存储器件和处理器之间提供并发通信的装置。 每个存储器件包括驱动器，相位/周期调整感测电路和总线对准通信逻辑。 每个相位/周期调整感测电路检测来自存储器件内相应的驱动器的周期调整的发生。 如果已经检测到循环调整的发生，则总线对准通信逻辑将处理器的循环调整的发生传达给处理器。 总线对准通信逻辑还将循环调整的发生与其他存储器件中的总线对准通信逻辑进行通信。 处理器内有多个接收器，并且每个接收器被设计成从存储器设备中的相应驱动器接收数据。 每个接收器包括循环延迟块。 接收到发生循环调整的接收器通知其他接收机没有接收周期调整的发生，以使用它们的周期延迟块来延迟输入数据至少一个周期。

公开(公告)号：US06678814B2

公开(公告)日：2004-01-13

申请号：US09895225

申请日：2001-06-29

申请人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

发明人： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy ,  William John Starke

IPC分类号： G06F1202

CPC分类号： G06F12/0223 ,  G06F9/5016

摘要： An apparatus for allocating data usage in an embedded dynamic random access memory (DRAM) device is disclosed. The apparatus for allocating data usages within an embedded dynamic random access memory (DRAM) device comprises a control analysis circuit, a data/command flow circuit, and a partition management control. The control analysis circuit generates an allocation signal in response to processing performances of a processor. Coupled to an embedded DRAM device, the data/command flow circuit controls data flow from the processor to the embedded DRAM device. The partition management control, coupled to the control analysis circuit, partitions the embedded DRAM device into a first partition and a second partition. The data stored in the first partition are different from the data stored in the second partition according to their respective usage. The allocation percentages of the first and second partitions are dynamically allocated by the allocation signal from the control analysis circuit.

摘要翻译： 公开了一种用于在嵌入式动态随机存取存储器（DRAM）装置中分配数据使用的装置。 用于在嵌入式动态随机存取存储器（DRAM）装置内分配数据用途的装置包括控制分析电路，数据/命令流电路和分区管理控制。 控制分析电路根据处理器的处理性能生成分配信号。 耦合到嵌入式DRAM设备，数据/命令流程电路控制从处理器到嵌入式DRAM设备的数据流。 耦合到控制分析电路的分区管理控制将嵌入式DRAM设备分割成第一分区和第二分区。 存储在第一分区中的数据根据​​它们各自的用途而不同于存储在第二分区中的数据。 通过来自控制分析电路的分配信号动态分配第一和第二分区的分配百分比。

公开(公告)号：US06467030B1

公开(公告)日：2002-10-15

申请号：US09435962

申请日：1999-11-09

申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy

发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  James Stephen Fields, Jr. ,  Sanjeev Ghai ,  Praveen S. Reddy

IPC分类号： G06F1200

CPC分类号： G06F12/0897 ,  G06F12/0862 ,  G06F2212/6022

摘要： A method and apparatus for forwarding data in a hierarchial cache memory architecture is disclosed. A cache memory hierarchy includes multiple levels of cache memories, each level having a different size and speed. A command is initially issued from a processor to the cache memory hierarchy. If the command is a Demand Load command, data corresponding to the Demand Load command is immediately forwarded from a cache having the data to the processor. Otherwise, if the command is a Prefetch Load command, data corresponding to the Prefetch Load command is held in a cache reload buffer within a cache memory preceding the processor.

摘要翻译： 公开了一种用于在分级高速缓冲存储器架构中转发数据的方法和装置。 高速缓冲存储器层级包括多级缓存存储器，每级具有不同的大小和速度。 命令最初从处理器发出到高速缓存存储器层次结构。 如果命令是Demand Load命令，则与Demand Load命令相对应的数据将立即从具有数据的缓存转发到处理器。 否则，如果命令是预取加载命令，则与预取加载命令对应的数据保存在处理器之前的高速缓存中的缓存重新加载缓冲区中。

公开(公告)号：US06457085B1

公开(公告)日：2002-09-24

申请号：US09434764

申请日：1999-11-04

申请人： Praveen S. Reddy

发明人： Praveen S. Reddy

IPC分类号： G06F1338

CPC分类号： G06F13/161 ,  G06F12/0813 ,  G06F12/0831 ,  G06F13/1657

摘要： A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, functionality for address paths and data paths are implemented in the node controller and are implemented in physically separate components. Commands are sent from the node address controller to the node data controller to control the flow of data through a node.

摘要翻译： 提供了一种使用基于总线的高速缓存相干协议的大方向对称多处理器系统的分布式系统结构。 分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备。 节点控制器从主设备接收命令，与主设备作为另一个主设备或从设备通信，并对从主设备接收的命令进行排队。 由于可能由大型总线引起的引脚限制，地址路径和数据路径的功能在节点控制器中实现，并且在物理上分离的组件中实现。 命令从节点地址控制器发送到节点数据控制器，以控制通过节点的数据流。

公开(公告)号：US07886199B2

公开(公告)日：2011-02-08

申请号：US12332511

申请日：2008-12-11

申请人： James S. Fields, Jr. ,  Benjiman L. Goodman ,  Praveen S. Reddy

发明人： James S. Fields, Jr. ,  Benjiman L. Goodman ,  Praveen S. Reddy

IPC分类号： G06F11/00

CPC分类号： G06F11/0751 ,  G06F11/076 ,  G06F11/0793

摘要： A data processing system, method, and computer-usable medium for recovering from a hang condition in a data processing system. The data processing system includes a collection of coupled processing units. The processing units include a collection of processing unit components such as, two or more processing cores, and a cache array, a processor core master, a cache snooper, and a local hang manager. The local hang manager determines whether at least one component out of the collection of processing unit components has entered into a hang condition. If the local hang manager determines at least one component has entered into a hang condition, a throttling manager throttles the performance of the processing unit in an attempt to break the at least one component out of the hang condition.

摘要翻译： 一种用于从数据处理系统中的挂起状态恢复的数据处理系统，方法和计算机可用介质。 数据处理系统包括耦合处理单元的集合。 处理单元包括诸如两个或更多个处理核心的处理单元组件的集合，以及高速缓存阵列，处理器核心主控器，高速缓存侦听器和本地挂起管理器。 本地挂起管理器确定处理单元组件的集合中的至少一个组件是否已进入挂起状态。 如果本地挂起管理器确定至少有一个组件已进入挂起状态，则节流管理器会阻止处理单元的性能，以试图将至少一个组件从挂起状态中断。

公开(公告)号：US20090132791A1

公开(公告)日：2009-05-21

申请号：US12332511

申请日：2008-12-11

申请人： James S. Fields, Jr. ,  Benjiman L. Goodman ,  Praveen S. Reddy

发明人： James S. Fields, Jr. ,  Benjiman L. Goodman ,  Praveen S. Reddy

IPC分类号： G06F9/318

CPC分类号： G06F11/0751 ,  G06F11/076 ,  G06F11/0793

摘要： A data processing system, method, and computer-usable medium for recovering from a hang condition in a data processing system. The data processing system includes a collection of coupled processing units. The processing units include a collection of processing unit components such as, two or more processing cores, and a cache array, a processor core master, a cache snooper, and a local hang manager. The local hang manager determines whether at least one component out of the collection of processing unit components has entered into a hang condition. If the local hang manager determines at least one component has entered into a hang condition, a throttling manager throttles the performance of the processing unit in an attempt to break the at least one component out of the hang condition.

摘要翻译： 一种用于从数据处理系统中的挂起状态恢复的数据处理系统，方法和计算机可用介质。 数据处理系统包括耦合处理单元的集合。 处理单元包括诸如两个或更多个处理核心的处理单元组件的集合，以及高速缓存阵列，处理器核心主控器，高速缓存侦听器和本地挂起管理器。 本地挂起管理器确定处理单元组件的集合中的至少一个组件是否已进入挂起状态。 如果本地挂起管理器确定至少有一个组件已进入挂起状态，则节流管理器会阻止处理单元的性能，以试图将至少一个组件从挂起状态中断。

公开(公告)号：US07484131B2

公开(公告)日：2009-01-27

申请号：US11225639

申请日：2005-09-13

申请人： James S. Fields, Jr. ,  Benjiman L. Goodman ,  Praveen S. Reddy

发明人： James S. Fields, Jr. ,  Benjiman L. Goodman ,  Praveen S. Reddy

IPC分类号： G06F11/00

CPC分类号： G06F11/0751 ,  G06F11/076 ,  G06F11/0793

摘要： A data processing system, method, and computer-usable medium for recovering from a hang condition in a data processing system. The data processing system includes a collection of coupled processing units. The processing units include a collection of processing unit components such as, two or more processing cores, and a cache array, a processor core master, a cache snooper, and a local hang manager. The local hang manager determines whether at least one component out of the collection of processing unit components has entered into a hang condition. If the local hang manager determines at least one component has entered into a hang condition, a throttling manager throttles the performance of the processing unit in an attempt to break the at least one component out of the hang condition.

摘要翻译： 一种用于从数据处理系统中的挂起状态恢复的数据处理系统，方法和计算机可用介质。 数据处理系统包括耦合处理单元的集合。 处理单元包括诸如两个或更多个处理核心的处理单元组件的集合，以及高速缓存阵列，处理器核心主控器，高速缓存侦听器和本地挂起管理器。 本地挂起管理器确定处理单元组件的集合中的至少一个组件是否已进入挂起状态。 如果本地挂起管理器确定至少有一个组件已进入挂起状态，则节流管理器会阻止处理单元的性能，以试图将至少一个组件从挂起状态中断。