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1.发明授权Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique 有权使用延迟惩罚估计技术将驱动器大小合并到缓冲器插入中的装置和方法公开(公告)号：US06915496B2
公开(公告)日：2005-07-05
申请号：US10255469
申请日：2002-09-26
申请人： Charles Jay Alpert , Chong-Nuen Chu , Rama Gopal Gandham , Milos Hrkic , Jiang Hu , Chandramouli V. Kashyap , Stephen Thomas Quay
发明人： Charles Jay Alpert , Chong-Nuen Chu , Rama Gopal Gandham , Milos Hrkic , Jiang Hu , Chandramouli V. Kashyap , Stephen Thomas Quay
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： An apparatus and method for incorporating driver sizing into buffer insertion such that the two optimization techniques are performed simultaneously are provided. The apparatus and method extends van Ginneken's algorithm to handle driver sizing by treating a source node as a “driver library.” With the apparatus and method, the circuit design is converted to a Steiner tree representation of the circuit design. Buffer insertion is performed on the Steiner tree using the van Ginneken algorithm to generate a first set of possible optimal solutions. For each solution in the first set, a driver of the same type as the original driver in the Steiner tree is selected from a driver library and virtually inserted into the solution. A delay penalty is retrieved for the selected driver, which is then used long with the new driver's characteristics to generate a second set of solutions based o the first set of solutions.
摘要翻译： 提供了一种用于将驱动程序大小合并到缓冲器插入中以便同时执行两种优化技术的装置和方法。 该装置和方法扩展了van Ginneken的算法，通过将源节点视为“驱动程序库”来处理驱动程序大小。 利用该装置和方法，将电路设计转换为电路设计的Steiner树表示。 使用van Ginneken算法在Steiner树上执行缓冲区插入，以生成第一组可能的最优解。 对于第一组中的每个解决方案，从驱动程序库中选择与Steiner树中的原始驱动程序相同类型的驱动程序，并将其虚拟插入到解决方案中。 对于所选择的驱动程序检索延迟罚分，随后利用新驱动程序的特性，利用第一组解决方案生成第二组解决方案。
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2.发明授权Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management 有权使用同时阻止避免，延迟优化和设计密度管理来生成塞纳树的方法和装置公开(公告)号：US07127696B2
公开(公告)日：2006-10-24
申请号：US10738711
申请日：2003-12-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/505
摘要： A mechanism for constructing Steiner trees using simultaneous blockage avoidance, delay optimization, and design density management are provided. An initial tiled timing-driven Steiner tree is obtained for an integrated circuit design. The Steiner tree is broken into 2-paths for which plates are generated designated the permissible area in which a Steiner point may migrate. Each 2-path is optimized by calculating a cost for each tile in the plate as a function of an environmental cost, a tile delay cost, and a trade-off value. A minimum cost tile is then selected as the point to which the Steiner point in the 2-path, if any, is to migrate. Once each 2-path is processed in this manner, routing is performed so as to minimize the cost at the source. This process may be iteratively repeated with new trade-off values until all of the nets have zero or positive slew.
摘要翻译： 提供了一种使用同时阻止避免，延迟优化和设计密度管理构建Steiner树的机制。 获得用于集成电路设计的初始平铺时序驱动的Steiner树。 Steiner树被分解为2路径，其中生成了板，指定Steiner点可能迁移的允许区域。 通过根据环境成本，瓦片延迟成本和折衷值计算板中每个瓦片的成本来优化每个2路径。 然后选择最小成本图块作为2路径中Steiner点（如果有）要迁移的点。 一旦以这种方式处理了每个2路径，就执行路由以最小化源的成本。 可以用新的权衡值迭代地重复该过程，直到所有网络具有零或正的摆动。
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公开(公告)号：US07065730B2
公开(公告)日：2006-06-20
申请号：US10418469
申请日：2003-04-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method, computer program product, and data processing system for porosity-aware buffered Steiner tree construction are disclosed. A preferred embodiment begins with a timing-driven Steiner tree generated without regard for porosity, then applies a plate-based adjustment guided by length-based buffer insertion. After performing localized blockage avoidance, the resulting tree is then passed to a buffer placement algorithm, such as van Ginneken's algorithm, to obtain a porosity-aware buffered Steiner tree.
摘要翻译： 公开了一种用于孔隙度感知缓冲Steiner树结构的方法，计算机程序产品和数据处理系统。 优选实施例从不考虑孔隙率产生的定时驱动的Steiner树开始，然后施加基于长度的缓冲器插入引导的基于板的调整。 在执行局部阻止避免之后，所得到的树然后被传递到缓冲器放置算法，例如van Ginneken的算法，以获得孔隙度感知缓冲的Steiner树。
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公开(公告)号：US06898774B2
公开(公告)日：2005-05-24
申请号：US10324732
申请日：2002-12-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method, computer program product, and data processing system for inserting buffers into integrated circuit routing trees are disclosed. The present invention dynamically modifies a Steiner tree configuration as needed to derive a maximal slack solution that takes into account blockages such as those presented by IP blocks.
摘要翻译： 公开了一种用于将缓冲器插入到集成电路布线树中的方法，计算机程序产品和数据处理系统。 本发明根据需要动态地修改Steiner树配置以导出考虑到由IP块所呈现的阻塞的最大松弛解决方案。
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公开(公告)号：US06591411B2
公开(公告)日：2003-07-08
申请号：US09810075
申请日：2001-03-15
申请人： Charles Jay Alpert , Rama Gopal Gandham , Jiang Hu , Stephen Thomas Quay , Andrew James Sullivan
发明人： Charles Jay Alpert , Rama Gopal Gandham , Jiang Hu , Stephen Thomas Quay , Andrew James Sullivan
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , G06F17/505 , Y10S977/731
摘要： An apparatus and method for determining buffered Steiner trees for complex circuits is provided. The apparatus and method first clusters sinks with similar characteristics such as criticality, polarity and distance. The purpose of this step is to potentially isolate positive sinks from negative ones and non-critical sinks from critical ones. The present invention then constructs low-level Steiner trees over each of these clusters. Finally, a top-level timing driven Steiner tree is computed where each cluster is treated as a sink. The top-level tree is then merged with the low-level trees to yield a solution for the entire net.
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6.发明授权Method and system for re-routing interconnects within an integrated circuit design having blockages and bays 失效在具有阻塞和间隔的集成电路设计中重新布线互连的方法和系统公开(公告)号：US06401234B1
公开(公告)日：2002-06-04
申请号：US09465294
申请日：1999-12-17
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method and system for re-routing interconnects within an integrated circuit design having blockages and bays is disclosed. A net within the integrated circuit design is initially decomposed into multiple two-paths. The net includes interconnects previously routed by utilizing a Steiner tree routing algorithm. Next, a cost associated with each of the two-paths is calculated. A two-path having a a high cost is subsequently selected and re-routed with a lower cost two-path.
摘要翻译： 公开了一种用于在具有阻塞和间隔的集成电路设计中重新路由互连的方法和系统。 集成电路设计中的网络最初分解成多个双向路径。 网络包括先前通过利用Steiner树路由算法路由的互连。 接下来，计算与每个双向路径相关联的成本。 随后选择具有高成本的双路径并以较低成本的双路径重新路由。
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7.发明授权Apparatus and method for buffer library selection for use in buffer insertion 有权用于缓冲区插入的缓冲库选择的装置和方法公开(公告)号：US06560752B1
公开(公告)日：2003-05-06
申请号：US09611670
申请日：2000-07-06
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： An apparatus and method for buffer selection for use in buffer insertion is provided. An optimal buffer library generator module operates to reduce a general buffer library down to a optimal buffer library based on parameters that are input to the optimal buffer library generator module. Based on these parameters, the optimal buffer library generator module selects buffers from the general buffer library for inclusion in an optimal buffer library. In a preferred embodiment, the optimal buffer library is generated by generating a set of superior buffers and inverters and clustering the set of superior buffers. A single buffer is then selected from each cluster for inclusion in the optimal buffer library. The result is a smaller buffer library which will provide approximately the same performance during buffer insertion while reducing the amount of computing time and memory requirements.
摘要翻译： 提供了用于缓冲器插入的缓冲器选择的装置和方法。 最佳缓冲库生成器模块可以根据输入到最优缓冲库生成器模块的参数，将通用缓冲库减少到最佳缓冲库。 基于这些参数，最优缓冲库生成器模块从通用缓冲库中选择缓冲区以包含在最优缓冲库中。 在优选实施例中，通过生成一组优越的缓冲器和反相器并对该组优越的缓冲器进行聚类来生成最佳缓冲器库。 然后从每个簇选择单个缓冲区以包含在最佳缓冲库中。 结果是一个较小的缓冲库，在缓冲区插入期间将提供大致相同的性能，同时减少计算时间和内存需求量。
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8.发明授权Method and apparatus for performing density-biased buffer insertion in an integrated circuit design 有权在集成电路设计中执行密度偏置缓冲器插入的方法和装置公开(公告)号：US07137081B2
公开(公告)日：2006-11-14
申请号：US10738714
申请日：2003-12-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method, apparatus, and computer program product for performing density biased buffer insertion in an integrated circuit design are provided. A tiled Steiner tree topology map is used in which density values are associated with each tile in the map. A directed acyclic graph (DAG) is created over an initial set of potential candidate points. A subset of the candidate points is selected by associating costs with each tile, and with each path or edge, to each tile. The total costs associated with placement of a buffer at a position within each tile are calculated. The lowest cost tile is then selected as a candidate position for buffer insertion. This process is then repeated to obtain an asymmetrically distributed set of candidate buffer insertion points between a source and a sink.
摘要翻译： 提供了一种用于在集成电路设计中执行密度偏移缓冲器插入的方法，装置和计算机程序产品。 使用平铺的Steiner树拓扑图，其中密度值与地图中的每个图块相关联。 在一组初始潜在候选点上创建有向非循环图（DAG）。 通过将成本与每个瓦片相关联，并将每个路径或边缘与每个瓦片相关联来选择候选点的子集。 计算与在每个平铺内的位置放置缓冲区相关联的总成本。 然后选择最低成本图块作为缓冲区插入的候选位置。 然后重复该过程以获得在源和宿之间的不对称分布的候选缓冲区插入点集合。
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公开(公告)号：US06807659B2
公开(公告)日：2004-10-19
申请号：US10256104
申请日：2002-09-26
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： Physical design optimizations for integrated circuits, such as placement, buffer insertion, floorplanning and routing, require fast and accurate analysis of resistive-capacitive (RC) delays in the network. A method is disclosed for estimating delays at nodes in an RC circuit by calculating a first and second impulse response moments of the RC circuit, and matching the impulse response moments to a Weibull distribution. Based on the match, a signal delay value is computed. The invention may thus be used to determine whether the RC circuit meets a desired optimization condition, based on the signal delay value. In the exemplary implementation, the signal delay value at a delay point is calculated by finding a percentile of the Weibull distribution corresponding to the delay point. This implementation is accurate and very efficient as it uses only two very small look-up tables.
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10.发明授权Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model 失效使用有效电容量度（ECM）信号延迟模型确定互连延迟的方法和系统公开(公告)号：US06968306B1
公开(公告)日：2005-11-22
申请号：US09668320
申请日：2000-09-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for determining an interconnect delay at a node in an interconnect having a plurality of nodes. The method includes performing a bottom-up tree traversal to compute the first three admittance moments for each of the nodes in the interconnect. The computed admittance moments are utilized, in an advantageous embodiment, to compute a pi-model of the downstream load. Next, the equivalent effective capacitance value Ceff is computed utilizing the components of the computed pi-model and the Elmore delay at the node under evaluation. In an advantageous embodiment, Ceff is characterized by: Ceff=Cfj(1−e−T/τdj) where Cfj is the far-end capacitance of the pi-model at the node, T is the Elmore delay at the node and τdj is the resistance of the pi-model (Rdj) multiplied by Cfj. The interconnect delay at the node is then determined utilizing an effective capacitance metric (ECM) delay model.
摘要翻译： 一种用于确定具有多个节点的互连中的节点处的互连延迟的方法。 该方法包括执行自下而上的树遍历，以计算互连中每个节点的前三个导纳矩。 在有利的实施例中，计算的导纳矩被用于计算下游负载的pi模型。 接下来，使用计算的pi模型的分量和在评估节点处的Elmore延迟来计算等效有效电容值C eff。 在有利的实施方案中，C eff的特征在于：<？in-line-formula description =“In-line Formulas”end =“lead”？> C eff = （1-e -T / taudj）<？in-line-formula description =“In-line Formulas”end =“tail”？>其中C < SUB> fj 是节点处的pi模型的远端电容，T是节点处的Elmore延迟，taudj是pi模型的电阻（R SUB dj ）乘以C 。 然后使用有效电容量度（ECM）延迟模型来确定节点处的互连延迟。
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