公开(公告)号：US06560752B1

公开(公告)日：2003-05-06

申请号：US09611670

申请日：2000-07-06

申请人： Charles Jay Alpert ,  Rama Gopal Gandham ,  Jose Luis Pontes Correia Neves ,  Stephen Thomas Quay

发明人： Charles Jay Alpert ,  Rama Gopal Gandham ,  Jose Luis Pontes Correia Neves ,  Stephen Thomas Quay

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： An apparatus and method for buffer selection for use in buffer insertion is provided. An optimal buffer library generator module operates to reduce a general buffer library down to a optimal buffer library based on parameters that are input to the optimal buffer library generator module. Based on these parameters, the optimal buffer library generator module selects buffers from the general buffer library for inclusion in an optimal buffer library. In a preferred embodiment, the optimal buffer library is generated by generating a set of superior buffers and inverters and clustering the set of superior buffers. A single buffer is then selected from each cluster for inclusion in the optimal buffer library. The result is a smaller buffer library which will provide approximately the same performance during buffer insertion while reducing the amount of computing time and memory requirements.

摘要翻译： 提供了用于缓冲​​器插入的缓冲器选择的装置和方法。 最佳缓冲库生成器模块可以根据输入到最优缓冲库生成器模块的参数，将通用缓冲库减少到最佳缓冲库。 基于这些参数，最优缓冲库生成器模块从通用缓冲库中选择缓冲区以包含在最优缓冲库中。 在优选实施例中，通过生成一组优越的缓冲器和反相器并对该组优越的缓冲器进行聚类来生成最佳缓冲器库。 然后从每个簇选择单个缓冲区以包含在最佳缓冲库中。 结果是一个较小的缓冲库，在缓冲区插入期间将提供大致相同的性能，同时减少计算时间和内存需求量。

公开(公告)号：US07895539B2

公开(公告)日：2011-02-22

申请号：US11873919

申请日：2007-10-17

申请人： Christopher Carney ,  Jose Luis Pontes Correia Neves ,  Biagio Pluchino

发明人： Christopher Carney ,  Jose Luis Pontes Correia Neves ,  Biagio Pluchino

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505

摘要： A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of the plurality of nets. The logic circuit analyzer may determine a slack-value for each net. In addition, the logic circuit analyzer may selectively reduce resistive-capacitive delay for each net respectively if the determined slack-value is less than the target slack-value for each respective net.

摘要翻译： 用于改进逻辑电路的系统可以包括处理器和与处理器通信以对多个网络建模的逻辑电路分析器。 该系统还可以包括与逻辑电路分析器通信的接口，以针对多个网络中的每一个网络选择目标松弛值。 逻辑电路分析器可以确定每个网络的松弛值。 此外，如果确定的松弛值小于每个相应网的目标松弛值，则逻辑电路分析器可以分别选择性地减小每个网络的电阻 - 电容延迟。

公开(公告)号：US07979838B2

公开(公告)日：2011-07-12

申请号：US12032517

申请日：2008-02-15

申请人： Christopher J. Berry ,  Jose Luis Pontes Correia Neves ,  Lawrence David Curley ,  Patrick James Meaney ,  Travis Wellington Pouarz ,  William J. Scarpero, Jr.

发明人： Christopher J. Berry ,  Jose Luis Pontes Correia Neves ,  Lawrence David Curley ,  Patrick James Meaney ,  Travis Wellington Pouarz ,  William J. Scarpero, Jr.

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/62

摘要： The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.

摘要翻译： 在集成芯片设计中布置时钟控制分配网络的平面图的过程被简化，并且提高了创建分段网络的效率。 在Cadence Viewer中查看芯片平面图的图片时，不是在HDL中手动创建分段网络，也可以将其作为网络描述表，在Cadence环境中运行的自动化方法使用算法方法来最大限度地利用 分段锁存器，消除不必要的电源和区域使用。 通过使用算法到达的分段解决方案直接更新物理布局来最大化效率。

公开(公告)号：US06651230B2

公开(公告)日：2003-11-18

申请号：US09683276

申请日：2001-12-07

申请人： John Maxwell Cohn ,  Jose Luis Pontes Correia Neves ,  Paul Steven Zuchowski

发明人： John Maxwell Cohn ,  Jose Luis Pontes Correia Neves ,  Paul Steven Zuchowski

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F1/10

摘要： A method for reducing the effect of signal skew degradation in the design of an integrated circuit is provided. First, a circuit design library is created describing library cells as a function of one or more environmental variable, wherein the one or more environmental variable includes a skew degradation variable indicating skew degradation of a signal as a function of a total number of signal switches of the signal. Then, the integrated circuit design is modeled utilizing the circuit design library to determine a first skew degradation for each of the first and second signals at a first predetermined number of signal switches, and a second skew degradation for each of the first and second signals for a second predetermined number of signal switches, and further to determine a first relative skew degradation for a first predetermined number of signal switches and a second relative skew degradation for a second predetermined number of signal switches, wherein a relative skew degradation is equal to the difference of the skew degradation of the first signal and the skew degradation of the second signal for a given number of signal switches. Next, a skew shift equal to the difference between the first relative skew degradation and the second relative skew degradation is calculated. Finally, the integrated circuit design is modified such that a skew degradation of the first signal at the first predetermined number of signal switches is determined to be equal to the first skew degradation of the first signal minus half of the skew shift.

摘要翻译： 提供了一种降低集成电路设计中的信号偏差劣化的方法。 首先，创建描述作为一个或多个环境变量的函数的库单元的电路设计库，其中所述一个或多个环境变量包括歪斜劣化变量，其指示作为信号开关总数的函数的信号的歪斜退化 信号。 然后，使用电路设计库对集成电路设计进行建模，以在第一预定数量的信号开关处确定第一和第二信号中的每一个的第一偏斜劣化，以及用于第一和第二信号中的每一个的第二偏斜劣化 第二预定数量的信号开关，并且还用于确定第一预定数量的信号开关的第一相对偏斜劣化和第二预定数量的信号开关的第二相对偏斜劣化，其中相对偏斜劣化等于差 对于给定数量的信号开关，第一信号的偏斜劣化和第二信号的偏斜劣化。 接下来，计算等于第一相对偏斜劣化和第二相对偏斜劣化之间的差的偏移偏移。 最后，对集成电路设计进行修改，使得第一预定数量的信号开关处的第一信号的偏斜劣化被确定为等于第一信号的第一偏斜劣化减去偏移偏移的一半。