公开(公告)号：US06831635B2

公开(公告)日：2004-12-14

申请号：US09796885

申请日：2001-03-01

申请人： Charles N. Boyd ,  Jeff M. J. Noyle ,  Michael A. Toelle

发明人： Charles N. Boyd ,  Jeff M. J. Noyle ,  Michael A. Toelle

IPC分类号： G06F1700

CPC分类号： G06F9/541

摘要： A method for controlling the algorithmic elements in 3D graphics systems via an improved 3D graphics API is provided. In one aspect, the invention unifies separately provided 2D and 3D graphics APIs into a single graphics interface, thereby eliminating redundancy of functionality and unnecessary data types. As a result, a single mapping to various graphics objects replaces redundant mappings. A single texture download that optimizes the use of different graphics hardware is provided. A single instruction for effecting a resolution change is also provided.

摘要翻译： 提供了一种通过改进的3D图形API来控制3D图形系统中的算法元素的方法。 在一个方面，本发明将单独提供的2D和3D图形API统一为单个图形接口，从而消除功能冗余和不必要的数据类型。 因此，对各种图形对象的单一映射将替代冗余映射。 提供了优化不同图形硬件使用的单一纹理下载。 还提供了一个用于进行分辨率改变的指令。

公开(公告)号：US07570267B2

公开(公告)日：2009-08-04

申请号：US10934249

申请日：2004-09-03

申请人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

发明人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

IPC分类号： G06T1/00 ,  G06T15/00

CPC分类号： G06T15/005

摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.

摘要翻译： 提供了增强的图形流水线，其使公共核心硬件能够执行图形流水线的不同组件，由流水线中的组件包括线和三角形的原语的可编程性，以及在呈现与图形显示之间的流输出 数据在管道中。 编程人员不必优化代码，因为通用核心将平衡所需功能的负载，并在通用核心硬件上动态分配这些指令。 程序员可以使用算法编程原语，以通过用线和三角形进行拓扑替换来简化所有顶点计算。 程序员获取计算的输出数据，并在渲染之前或期间读取它们。 因此，程序员在编程中具有更大的灵活性。 通过使用增强型图形管线，程序员可以优化管道中硬件的使用，程序顶点，线或三角形拓扑，而不是单独使用每个顶点，并从管道可以输出计算的信息的内存读取任何计算的数据。

公开(公告)号：US09064334B2

公开(公告)日：2015-06-23

申请号：US13152452

申请日：2011-06-03

申请人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

发明人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

IPC分类号： G09G5/00 ,  G06T15/00 ,  G09G5/36 ,  G06T15/80 ,  G06T1/20 ,  G06T15/50

CPC分类号： G06T15/005 ,  G06T1/20 ,  G06T15/00 ,  G06T15/20 ,  G06T15/50 ,  G06T15/80 ,  G09G5/363

摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.

公开(公告)号：US07978205B1

公开(公告)日：2011-07-12

申请号：US10933850

申请日：2004-09-03

申请人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

发明人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

IPC分类号： G09G5/00

CPC分类号： G06T15/005 ,  G06T1/20 ,  G06T15/00 ,  G06T15/20 ,  G06T15/50 ,  G06T15/80 ,  G09G5/363

摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.

摘要翻译： 提供了增强的图形流水线，其使公共核心硬件能够执行图形流水线的不同组件，由流水线中的组件包括线和三角形的原语的可编程性，以及在呈现与图形显示之间的流输出 数据在管道中。 编程人员不必优化代码，因为通用核心将平衡所需功能的负载，并在通用核心硬件上动态分配这些指令。 程序员可以使用算法编程原语，以通过用线和三角形进行拓扑替换来简化所有顶点计算。 程序员获取计算的输出数据，并在渲染之前或期间读取它们。 因此，程序员在编程中具有更大的灵活性。 通过使用增强型图形管线，程序员可以优化管道中硬件的使用，程序顶点，线或三角形拓扑，而不是单独使用每个顶点，并从管道可以输出计算的信息的内存读取任何计算的数据。

公开(公告)号：US07671862B1

公开(公告)日：2010-03-02

申请号：US10934241

申请日：2004-09-03

申请人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

发明人： Amar Patel ,  Charles N. Boyd ,  David R. Blythe ,  Jeff M. J. Noyle ,  Michael A. Toelle ,  Stephen Harry Wright

IPC分类号： G06F15/00 ,  G06T1/00 ,  G06T1/20

CPC分类号： G06T15/005 ,  G06T1/20 ,  G06T15/00 ,  G06T15/20 ,  G06T15/50 ,  G06T15/80 ,  G09G5/363

摘要： An enhanced graphics pipeline is provided that enables common core hardware to perform as different components of the graphics pipeline, programmability of primitives including lines and triangles by a component in the pipeline, and a stream output before or simultaneously with the rendering a graphical display with the data in the pipeline. The programmer does not have to optimize the code, as the common core will balance the load of functions necessary and dynamically allocate those instructions on the common core hardware. The programmer may program primitives using algorithms to simplify all vertex calculations by substituting with topology made with lines and triangles. The programmer takes the calculated output data and can read it before or while it is being rendered. Thus, a programmer has greater flexibility in programming. By using the enhanced graphics pipeline, the programmer can optimize the usage of the hardware in the pipeline, program vertex, line or triangle topologies altogether rather than each vertex alone, and read any calculated data from memory where the pipeline can output the calculated information.

摘要翻译： 提供了增强的图形流水线，其使公共核心硬件能够执行图形流水线的不同组件，由流水线中的组件包括线和三角形的原语的可编程性，以及在呈现与图形显示之间的流输出 数据在管道中。 编程人员不必优化代码，因为通用核心将平衡所需功能的负载，并在通用核心硬件上动态分配这些指令。 程序员可以使用算法编程原语，以通过用线和三角形进行拓扑替换来简化所有顶点计算。 程序员获取计算的输出数据，并在渲染之前或期间读取它们。 因此，程序员在编程中具有更大的灵活性。 通过使用增强型图形管线，程序员可以优化管道中硬件的使用，程序顶点，线或三角形拓扑，而不是单独使用每个顶点，并从管道可以输出计算的信息的内存中读取任何计算的数据。

公开(公告)号：US20100039430A1

公开(公告)日：2010-02-18

申请号：US12604102

申请日：2009-10-22

申请人： Charles N. Boyd ,  Michael A. Toelle

发明人： Charles N. Boyd ,  Michael A. Toelle

IPC分类号： G06T15/50

CPC分类号： G06T15/005

摘要： An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.

摘要翻译： 提供了一种能够实现3D芯片的可编程性的API，其中由开发者编写的编程或算法元素可以被下载到芯片，从而对芯片进行编程以执行这些算法。 开发人员将可下载的例程写入3D图形芯片。 还提供了一组与已经为开发人员编程的API相关联的算法元素，可以下载到可编程芯片以提高性能。 因此，开发人员可以将预先存在的API对象下载到3D图形芯片。 开发人员坚持使用特定格式来打包一个由3D图形芯片实现的算法元素或指令集。 开发人员通过参考3D图形芯片了解的“令牌”列表将指令集打包成数组。 这个数组依次被正确地映射到3D图形芯片，用于由3D图形芯片实现算法元素。

公开(公告)号：US08274517B2

公开(公告)日：2012-09-25

申请号：US10986586

申请日：2004-11-12

申请人： Charles N. Boyd ,  Michele B. Boland ,  Michael A. Toelle ,  Anantha Rao Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen H. Wright

发明人： Charles N. Boyd ,  Michele B. Boland ,  Michael A. Toelle ,  Anantha Rao Kancherla ,  Amar Patel ,  Iouri Tarassov ,  Stephen H. Wright

IPC分类号： G06T1/00 ,  G06T15/00

CPC分类号： G06F9/325 ,  G06F9/3842 ,  G06F9/3879 ,  G06T15/005 ,  G06T15/80

摘要： Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.

摘要翻译： 提供了将算法元素下载到协处理器的系统和方法以及相应的处理和通信技术。 对于改进的图形管线，本发明提供了一类协处理设备，诸如图形处理器单元（GPU），为抽象或虚拟机提供改进的能力，用于执行图形计算和渲染。 本发明允许对下载到协处理器的程序的运行时预测流控制，使得协处理器能够在程序执行期间包括可读写的片上存储元件的可索引阵列，为纹理和纹理贴图提供本地支持，并在 顶点着色器提供输入到顶点着色器的顶点着色器的分频，可选地支持流模值，在像素着色器上提供寄存器存储元素，并且与表示像素的“面”关联的存储相关联的接口提供顶点 着色器和像素着色器，具有更多的片上寄存器存储，并且能够接收比任何现有顶点或像素着色器更大的程序，并在顶点和像素着色器中提供32位浮点数支持。

公开(公告)号：US07800607B2

公开(公告)日：2010-09-21

申请号：US10971484

申请日：2004-10-22

申请人： Charles N. Boyd ,  Michael A. Toelle

发明人： Charles N. Boyd ,  Michael A. Toelle

IPC分类号： G06F17/00

CPC分类号： G06T15/005

摘要： An API is provided that enables programmability of a 3D chip, wherein programming or algorithmic elements written by the developer can be downloaded to the chip, thereby programming the chip to perform those algorithms. A developer writes a routine that is downloadable to a 3D graphics chip. There are also a set of algorithmic elements that are provided in connection with the API that have already been programmed for the developer, that are downloadable to the programmable chip for improved performance. Thus, a developer may download preexisting API objects to a 3D graphics chip. A developer adheres to a specific format for packing up an algorithmic element, or set of instructions, for implementation by a 3D graphics chip. The developer packs the instruction set into an array of numbers, by referring to a list of ‘tokens’ understood by the 3D graphics chip. This array of numbers in turn is mapped correctly to the 3D graphics chip for implementation of the algorithmic element by the 3D graphics chip.

公开(公告)号：US07324116B2

公开(公告)日：2008-01-29

申请号：US10176811

申请日：2002-06-20

申请人： Charles N. Boyd ,  Michael A. Toelle

发明人： Charles N. Boyd ,  Michael A. Toelle

IPC分类号： G09G5/00

CPC分类号： G06T15/04

摘要： Systems and methods are provided for controlling texture sampling in connection with computer graphics in a computer system. In various embodiments, improved mechanisms for controlling texture sampling are provided that enable 3-D accelerator hardware to greatly increase the level of realism in rendering, including improved mechanisms for (1) motion blur; (2) generating anisotropic surface reflections (3) generating surface self-shadowing (4) ray-cast volumetric sampling (4) self-shadowed volumetric rendering and (5) self-shadowed volumetric ray-casting. In supplementing existing texture sampling techniques, parameters for texture sampling may be replaced and/or modified.

摘要翻译： 提供系统和方法用于控制与计算机系统中的计算机图形相关的纹理采样。 在各种实施例中，提供了用于控制纹理采样的改进机制，其使3-D加速器硬件能够大大增加渲染中的逼真度，包括（1）运动模糊的改进机制; （2）产生各向异性表面反射（3）产生表面自阴影（4）射线体积采样（4）自阴影体积渲染和（5）自阴影体积射线铸造。 在补充现有的纹理采样技术中，用于纹理采样的参数可以被替换和/或修改。

公开(公告)号：US06819325B2

公开(公告)日：2004-11-16

申请号：US09801079

申请日：2001-03-06

申请人： Charles N. Boyd ,  Michael A. Toelle

发明人： Charles N. Boyd ,  Michael A. Toelle

IPC分类号： G09G536

CPC分类号： G06T15/00 ,  G06T15/005 ,  G06T15/80 ,  G06T2210/32

摘要： A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.

摘要翻译： 用于与具有本地寄存器的顶点着色器和像素着色器的硬件实现进行通信的三维API。 关于顶点着色器，提供可以利用片上寄存器索引的API通信，并且还为在寄存器级别片上实现的专用功能提​​供API通信，该专用功能输出片上寄存器索引的分数部分 输入（s）。 对于像素着色器，针对特定功能提供API通信，其在执行线性插值功能的寄存器级片上片上实现，并且还为在寄存器级别片上实现的专用修改器提供API通信， 执行修改功能，包括否定，补充，重新映射，粘贴偏移，缩放和饱和。 有利地，这些API通信将这些非常有用的片上图形算法元件暴露给开发者，同时隐藏来自开发者的顶点着色器和像素着色器芯片的操作的细节。