公开(公告)号：US20060182214A1

公开(公告)日：2006-08-17

申请号：US11056767

申请日：2005-02-11

申请人： Charlie Hwang ,  Timothy McNamara ,  Ching-Lung Tong ,  Wiren Becker

发明人： Charlie Hwang ,  Timothy McNamara ,  Ching-Lung Tong ,  Wiren Becker

IPC分类号： H04L7/02

CPC分类号： H03L7/06 ,  G06F1/10

摘要： A method of self-synchronizing clocks in a multiple chip system, by assigning one chip as the master chip and the other chips as slave chips. A training signal is sent from master chip to the slave chips to determine the latency from the master chip to a slave chip, and then a synchronization signal is sent out to synchronize the “time zero” of the chips.

摘要翻译： 一种在多芯片系统中自同步时钟的方法，通过分配一个芯片作为主芯片，将其它芯片分配为从芯片。 训练信号从主芯片发送到从芯片，以确定从主芯片到从芯片的延迟，然后发送同步信号以同步芯片的“时间零”。

公开(公告)号：US20060182212A1

公开(公告)日：2006-08-17

申请号：US11363871

申请日：2006-02-28

申请人： Charlie Hwang ,  Wiren Becker ,  Timothy McNamara ,  Ching-Lung Tong

发明人： Charlie Hwang ,  Wiren Becker ,  Timothy McNamara ,  Ching-Lung Tong

IPC分类号： H04L7/00

CPC分类号： G06F1/10 ,  H03L7/06

摘要： A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically. This invention resolves the uncertainty problem and allows the synchronization signals to be generated deterministically independent of the chip global clock cycle time

摘要翻译： 一种用于产生多芯片系统的同步信号的时钟发生器电路。 时钟发生器电路包括从参考时钟和具有边缘检测逻辑的芯片全局时钟产生同步信号。 在具有多个芯片的高性能服务器系统设计中，服务器系统的常见做法是使用反馈时钟和延迟参考时钟来生成同步信号。 所产生的同步信号被传送到由全局时钟计时的锁存器，以用于芯片同步功能。 随着系统时钟频率被推高，由反馈时钟所产生的所生成的同步信号与由全局时钟计时的接收锁存器之间的相位差成为这个信号不能被确定地传送的循环时间的大部分。 本发明解决了不确定性问题，并允许确定地产生同步信号，而不依赖于芯片全局时钟周期时间

公开(公告)号：US20070176653A1

公开(公告)日：2007-08-02

申请号：US11419224

申请日：2006-05-19

申请人： William Huott ,  Charlie Hwang ,  Timothy McNamara

发明人： William Huott ,  Charlie Hwang ,  Timothy McNamara

IPC分类号： H03K23/00

CPC分类号： G06F7/68 ,  H03K23/68

摘要： A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

摘要翻译： 用于在芯片上本地产生比率时钟的方法包括产生具有全局时钟周期的全局时钟信号。 集中式状态机包括响应于非整数数量的全局时钟周期的整个周期的计数器，状态机响应于计数器产生控制信号。 控制信号被提供给分段锁存器，分段锁存器产生时钟高信号和时钟低电平信号。 响应于全局时钟信号，时钟高电平信号和时钟低电平信号，本地通道门产生（n + 0.5）至1时钟信号。

公开(公告)号：US20070176651A1

公开(公告)日：2007-08-02

申请号：US11341032

申请日：2006-01-27

申请人： William Huott ,  Charlie Hwang ,  Timothy McNamara

发明人： William Huott ,  Charlie Hwang ,  Timothy McNamara

IPC分类号： H03K23/00

CPC分类号： H03K23/502

摘要： Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to−1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

摘要翻译： 用于在芯片上本地生成比率时钟的电路。 该电路包括用于产生具有全局时钟周期的全局时钟信号的电路。 状态机包括响应于非整数个全局时钟周期的整个周期的计数器。 状态机响应于计数器产生控制信号。 分段锁存器接收控制信号并产生时钟高信号和时钟低信号，时钟高信号和时钟低信号具有从目标分频比时钟的波形导出的模式，时钟高信号和时钟低信号具有 符合目标分频时钟频率和占空比的模式。 本地通过门接收时钟低电平信号和时钟高电平信号，并响应于全局时钟信号，时钟高电平信号和时钟低电平信号产生（n + 0.5）至1时钟信号。

公开(公告)号：US20080030246A1

公开(公告)日：2008-02-07

申请号：US11869935

申请日：2007-10-10

申请人： William Huott ,  Charlie Hwang ,  Timothy McNamara

发明人： William Huott ,  Charlie Hwang ,  Timothy McNamara

IPC分类号： H03L7/00

CPC分类号： H03K23/502

摘要： Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal. A local pass gate receives the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to at least one of the global clock signal, the clock high signal and the clock low signal.

摘要翻译： 用于在芯片上本地生成比率时钟的电路。 该电路包括用于产生具有全局时钟周期的全局时钟信号的电路。 状态机包括响应于非整数个全局时钟周期而经过整个周期的计数器，状态机响应于计数器产生控制信号。 分段锁存器接收控制信号并产生时钟高电平信号和时钟低电平信号。 响应于全局时钟信号，时钟高电平信号和时钟低电平信号中的至少一个，本地通道门接收时钟低电平信号和时钟高电平信号并产生（n + 0.5）至1时钟信号。

公开(公告)号：US20070176652A1

公开(公告)日：2007-08-02

申请号：US11341038

申请日：2006-01-27

申请人： William Huott ,  Charlie Hwang ,  Timothy McNamara

发明人： William Huott ,  Charlie Hwang ,  Timothy McNamara

IPC分类号： H03K23/00

CPC分类号： H03K23/68 ,  G06F7/68

摘要： A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock and the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle. Local pass gate are provided for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

摘要翻译： 用于在芯片上本地产生比率时钟的方法包括产生具有全局时钟周期的全局时钟信号。 提供集中式状态机，其包括响应于非整数数量的全局时钟周期的整个周期的计数器，所述集中式状态机响应于所述计数器产生控制信号。 控制信号被提供给分段锁存器，分段锁存器产生时钟高信号和时钟低信号，时钟高电平和时钟低电平信号具有从目标分频比时钟的波形导出的模式，以及时钟高电平和时钟低电平信号 具有匹配目标分频时钟频率和占空比的模式。 本地通路门用于响应于全局时钟信号，时钟高电平信号和时钟低电平信号产生（n + 0.5）至1时钟信号。

公开(公告)号：US20060242510A1

公开(公告)日：2006-10-26

申请号：US11336082

申请日：2006-01-20

申请人： Patrick Meaney ,  Timothy McNamara ,  Bryan Mechtly

发明人： Patrick Meaney ,  Timothy McNamara ,  Bryan Mechtly

IPC分类号： G01R31/28

CPC分类号： G11C29/78 ,  G01R31/318541

摘要： An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) testing. The method makes use of programmable fuses which contain Level Sensitive Scan Design (LSSD) latches which also have a system port. The system port allows for simpler reading of the fuses as well as for the dynamic updates of the programmable fuses for wordline and other repairs.

公开(公告)号：US20060095300A1

公开(公告)日：2006-05-04

申请号：US11312317

申请日：2005-12-20

申请人： Robert Schrier ,  John Gambertoglio ,  Francesca Aweeka ,  Douglas Schrier ,  Janet Austin ,  Cheryl Heiland ,  Timothy McNamara

发明人： Robert Schrier ,  John Gambertoglio ,  Francesca Aweeka ,  Douglas Schrier ,  Janet Austin ,  Cheryl Heiland ,  Timothy McNamara

IPC分类号： G06F19/00

CPC分类号： G06F19/3456 ,  G06F19/326 ,  G06Q50/24 ,  G16H10/60

摘要： Systems and methods for processing data relating to use of a drug by a patient that receive patient information and determine a dosage of the drug on the basis of the patient information. The systems and methods may be operated to provide patient-specific information on drug cost and on comparative costs of alternative drugs, on side effects, on allergies, and on pharmacology, as well as information on use in pregnancy, on use in lactation, on drug interactions, on warnings and contraindications, and supporting references. The systems may also be operated to prepare drug orders and prescriptions.

公开(公告)号：US20050149802A1

公开(公告)日：2005-07-07

申请号：US11013728

申请日：2004-12-16

申请人： Karin Rebmann ,  Dietmar Schmunkamp ,  Tobias Webel ,  Thomas Gilbert ,  Timothy McNamara ,  Patrick Meaney

发明人： Karin Rebmann ,  Dietmar Schmunkamp ,  Tobias Webel ,  Thomas Gilbert ,  Timothy McNamara ,  Patrick Meaney

IPC分类号： G01R31/28

CPC分类号： G06F11/0793 ,  G06F9/544 ,  G06F11/0709 ,  Y10S707/99931 ,  Y10S707/99939 ,  Y10S707/99943

摘要： The present invention provides a new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

摘要翻译： 本发明提供了一种新的多节点计算机系统，其包括不同类型的芯片所驻留的多个节点。 新的多节点计算机系统的特征在于每个节点有一个时钟芯片，每个时钟芯片仅控制驻留在该节点上的芯片，所述芯片适合于在发生故障的情况下向相关联的时钟芯片发送检查停止请求。 新的检查停止处理方法的特征在于，根据检查停止请求的来源，接收到检查停止请求的时钟芯片启动系统检查停止，节点检查或芯片检查停止。

公开(公告)号：US20060195288A1

公开(公告)日：2006-08-31

申请号：US11056874

申请日：2005-02-12

申请人： Timothy McNamara ,  Joseph Eckelman ,  William Huott

发明人： Timothy McNamara ,  Joseph Eckelman ,  William Huott

IPC分类号： G01R27/28

CPC分类号： G01R31/31727

摘要： A method of and system for testing multi clock domain devices at functional clock speed by aligning the Launching C2 clocks of the high speed and low speed domains, issuing a Cl->C2 clock in each domain, to at speed test all intra-domain paths and the low speed to high speed paths; aligning the capturing C1 clock edges of the high speed and low speed clocks; and issuing a C2->C1 clock in each domain, to test the high speed to low speed paths.

摘要翻译： 一种用于通过对齐高速和低速域的启动C2时钟，在每个域中发出Cl-> C2时钟来测试多时钟域设备的方法和系统，以速度测试所有域内路径 和低速到高速路径; 对齐高速和低速时钟的捕获C1时钟边沿; 并在每个域中发出C2-> C1时钟，以测试高速到低速路径。