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    Non-volatile memory (NVM) with imminent error prediction
    3.
    发明授权
    Non-volatile memory (NVM) with imminent error prediction 有权
    非易失性存储器（NVM）具有迫在眉睫的错误预测

    公开(公告)号：US08572445B2

    公开(公告)日：2013-10-29

    申请号：US12886861

    申请日：2010-09-21

    申请人： Richard K. Eguchi ,  Daniel Hadad ,  Chen He ,  Katrina M. Prosperi ,  Jon W. Weilemann, II

    发明人： Richard K. Eguchi ,  Daniel Hadad ,  Chen He ,  Katrina M. Prosperi ,  Jon W. Weilemann, II

    IPC分类号： G11C29/00

    CPC分类号： G11C29/38 ,  G06F11/073 ,  G06F11/0754 ,  G11C16/3418

    摘要： A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value.

    摘要翻译： 提供了一种用于确定非易失性存储器阵列即将发生故障的方法和系统。 该方法包括：执行存储器阵列的第一阵列完整性读取，直到检测到错误; 确定所述误差不是可纠正的纠错码（ECC），其中与所述误差相关联的第一字线电压被表征为第一阈值电压; 执行存储器阵列的第二阵列完整性读取，直到存储器阵列的所有位指示预定状态，其中与指示预定状态的所有位相关联的第二字线电压是第二阈值电压; 以及将所述第一阈值电压和所述第二阈值电压之间的差值比较为预定值。

    Non-volatile memory (NVM) with imminent error prediction
    4.
    发明授权
    Non-volatile memory (NVM) with imminent error prediction 有权
    非易失性存储器（NVM）具有迫在眉睫的错误预测

    公开(公告)号：US08782478B2

    公开(公告)日：2014-07-15

    申请号：US14048362

    申请日：2013-10-08

    申请人： Richard K. Eguchi ,  Daniel Hadad ,  Chen He ,  Katrina M. Prosperi ,  Jon W. Weilmann, II

    发明人： Richard K. Eguchi ,  Daniel Hadad ,  Chen He ,  Katrina M. Prosperi ,  Jon W. Weilmann, II

    IPC分类号： G11C29/00

    CPC分类号： G11C29/38 ,  G06F11/073 ,  G06F11/0754 ,  G11C16/3418

    摘要： A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.

    摘要翻译： 非易失性存储器系统包括存储器阵列和存储器控制器。 存储器控制器被配置为执行阵列的第一阵列完整性读取操作，直到检测到错误。 控制器还被配置为确定错误不是纠错码（ECC）可校正。 与误差相关联的第一字线电压被表征为第一阈值电压。 控制器还被配置为执行阵列的第二阵列完整性读操作。 第二阵列完整性读操作包括使用偏离第一阈值电压的字线读取电压读取阵列，并且基于预定的宽度偏移参考值。 最后，控制器被配置为检查由第二阵列完整性读操作产生的校验和值，以确定何时指示存储器阵列中即将发生的故障。

    Non-Volatile Memory (NVM) with Imminent Error Prediction
    5.
    发明申请
    Non-Volatile Memory (NVM) with Imminent Error Prediction 有权
    具有即时误差预测的非易失性存储器（NVM）

    公开(公告)号：US20140040687A1

    公开(公告)日：2014-02-06

    申请号：US14048362

    申请日：2013-10-08

    申请人： Richard K. Eguchi ,  Daniel Hadad ,  Chen He ,  Katrina M. Prosperi ,  Jon W. Weilmann, II

    发明人： Richard K. Eguchi ,  Daniel Hadad ,  Chen He ,  Katrina M. Prosperi ,  Jon W. Weilmann, II

    IPC分类号： G11C29/38

    CPC分类号： G11C29/38 ,  G06F11/073 ,  G06F11/0754 ,  G11C16/3418

    摘要： A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.

    摘要翻译： 非易失性存储器系统包括存储器阵列和存储器控制器。 存储器控制器被配置为执行阵列的第一阵列完整性读取操作，直到检测到错误。 控制器还被配置为确定错误不是纠错码（ECC）可校正。 与误差相关联的第一字线电压被表征为第一阈值电压。 控制器还被配置为执行阵列的第二阵列完整性读操作。 第二阵列完整性读操作包括使用偏离第一阈值电压的字线读取电压读取阵列，并且基于预定的宽度偏移参考值。 最后，控制器被配置为检查由第二阵列完整性读操作产生的校验和值，以确定何时指示存储器阵列中即将发生的故障。