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1.发明授权Method and apparatus for EEPROM emulation for preventing data loss in the event of a flash block failure 有权用于EEPROM仿真的方法和装置，用于防止闪存块发生故障时的数据丢失公开(公告)号：US08516213B2
公开(公告)日：2013-08-20
申请号：US12954130
申请日：2010-11-24
IPC分类号： G06F13/00
CPC分类号： G06F11/1666 , G06F12/0246 , G06F2212/7209
摘要： A defect resistant EEPROM emulator (110) uses one or more redundant and/or spare blocks (213) in addition to active and alternate blocks (211, 212) and stores a duplicate copy of EEPROM data records either in the active and redundant blocks or in duplicate rows in the active block to ensure that EEPROM emulation can continue without data loss in the event a catastrophic failure occurs within a block.
摘要翻译： 除了有源和交替块（211,212）之外，抗缺陷EEPROM仿真器（110）还使用一个或多个冗余和/或备用块（213），并将EEPROM数据记录的副本存储在主动和冗余块中 在活动块中重复一行，以确保在EEPROM中发生灾难性故障的情况下，EEPROM仿真可以继续而没有数据丢失。
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2.发明申请Method and Apparatus for EEPROM Emulation for Preventing Data Loss in the Event of a Flash Block Failure 有权用于在闪存块故障的情况下防止数据丢失的EEPROM仿真的方法和装置公开(公告)号：US20120131262A1
公开(公告)日：2012-05-24
申请号：US12954130
申请日：2010-11-24
IPC分类号： G06F12/02
CPC分类号： G06F11/1666 , G06F12/0246 , G06F2212/7209
摘要： A defect resistant EEPROM emulator (110) uses one or more redundant and/or spare blocks (213) in addition to active and alternate blocks (211, 212) and stores a duplicate copy of EEPROM data records either in the active and redundant blocks or in duplicate rows in the active block to ensure that EEPROM emulation can continue without data loss in the event a catastrophic failure occurs within a block.
摘要翻译： 除了有源和交替块（211,212）之外，抗缺陷EEPROM仿真器（110）还使用一个或多个冗余和/或备用块（213），并将EEPROM数据记录的副本存储在主动和冗余块中 在活动块中重复一行，以确保在EEPROM中发生灾难性故障的情况下，EEPROM仿真可以继续而没有数据丢失。
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公开(公告)号：US08572445B2
公开(公告)日：2013-10-29
申请号：US12886861
申请日：2010-09-21
IPC分类号： G11C29/00
CPC分类号： G11C29/38 , G06F11/073 , G06F11/0754 , G11C16/3418
摘要： A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value.
摘要翻译： 提供了一种用于确定非易失性存储器阵列即将发生故障的方法和系统。 该方法包括：执行存储器阵列的第一阵列完整性读取，直到检测到错误; 确定所述误差不是可纠正的纠错码（ECC），其中与所述误差相关联的第一字线电压被表征为第一阈值电压; 执行存储器阵列的第二阵列完整性读取，直到存储器阵列的所有位指示预定状态，其中与指示预定状态的所有位相关联的第二字线电压是第二阈值电压; 以及将所述第一阈值电压和所述第二阈值电压之间的差值比较为预定值。
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4.发明申请Imminent Read Failure Detection Based Upon Unacceptable Wear For NVM Cells 有权基于NVM单元不可接受的磨损的即时读取故障检测公开(公告)号：US20150309857A1
公开(公告)日：2015-10-29
申请号：US14262116
申请日：2014-04-25
CPC分类号： G06F11/1008 , G06F11/008 , G06F11/073 , G06F11/0757 , G06F11/1068 , G11C11/5642 , G11C16/349
摘要： Methods and systems are disclosed for imminent read failure detection based upon unacceptable wear for non-volatile memory (NVM) cells. In certain embodiments, a first failure time is recorded when a first diagnostic mode detects an uncorrectable error within the NVM cell array using a first set of read voltage levels below and above a normal read voltage level. A second failure time is recorded when a second diagnostic mode detects an uncorrectable error within the NVM cell array using a second set of read voltage levels below and above a normal read voltage level. The first and second failure times are then compared against a threshold wear time value to determine whether or not an imminent read failure is indicated. The diagnostic modes can be run separately for erased NVM cell distributions and programmed NVM cell distributions to provide separate wear rate determinations.
摘要翻译： 公开了基于非易失性存储器（NVM）单元的不可接受的磨损的迫在眉睫的读取故障检测的方法和系统。 在某些实施例中，当第一诊断模式使用低于和高于正常读取电压电平的第一组读取电压电平来检测NVM单元阵列内的不可校正错误时，记录第一故障时间。 当第二诊断模式使用低于和高于正常读取电压电平的第二组读取电压电平来检测NVM单元阵列内的不可校正错误时，记录第二个故障时间。 然后将第一和第二故障时间与阈值磨损时间值进行比较，以确定是否指示即将发生的读取故障。 诊断模式可以单独运行，用于擦除的NVM单元分布和编程的NVM单元分布，以提供单独的磨损率确定。
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5.发明授权Imminent read failure detection based upon changes in error voltage windows for NVM cells 有权基于NVM单元的误差电压窗口的变化的即时读取故障检测公开(公告)号：US09329933B2
公开(公告)日：2016-05-03
申请号：US14262157
申请日：2014-04-25
CPC分类号： G06F11/1008 , G06F11/008 , G06F11/073 , G06F11/0757 , G06F11/1068 , G11C11/5642 , G11C16/349 , G11C29/42
摘要： Methods and systems are disclosed for imminent read failure detection based upon changes in error voltage windows for non-volatile memory (NVM) cells. In certain embodiments, data stored within an array of NVM cells is checked at a first time using a diagnostic mode and high/low read voltage sweeps to determine a first error voltage window where high/low uncorrectable errors are detected. Stored data is then checked at a second time using the diagnostic mode and high/low read voltage sweeps to determine a second error voltage window where high/low uncorrectable errors are detected. The difference between the error voltage windows are then compared against a voltage difference threshold value to determine whether or not to indicate an imminent read failure condition. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.
摘要翻译： 公开了基于非易失性存储器（NVM）单元的误差电压窗口的变化的迫在眉睫的读取故障检测的方法和系统。 在某些实施例中，使用诊断模式和高/低读取电压扫描在第一时间检查存储在NVM单元阵列内的数据，以确定检测到高/低不可校正错误的第一误差电压窗口。 然后使用诊断模式和高/低读取电压扫描第二次检查存储的数据，以确定检测到高/低不可校正错误的第二误差电压窗口。 然后将误差电压窗口之间的差异与电压差阈值进行比较，以确定是否指示即将发生的读取故障状况。 可以使用地址排序器，纠错码（ECC）逻辑和偏置发生器来实现即将发生的故障检测。
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6.发明授权Imminent read failure detection based upon unacceptable wear for NVM cells 有权基于NVM单元不可接受的磨损的即时读取故障检测公开(公告)号：US09329932B2
公开(公告)日：2016-05-03
申请号：US14262116
申请日：2014-04-25
CPC分类号： G06F11/1008 , G06F11/008 , G06F11/073 , G06F11/0757 , G06F11/1068 , G11C11/5642 , G11C16/349
摘要： Methods and systems are disclosed for imminent read failure detection based upon unacceptable wear for non-volatile memory (NVM) cells. In certain embodiments, a first failure time is recorded when a first diagnostic mode detects an uncorrectable error within the NVM cell array using a first set of read voltage levels below and above a normal read voltage level. A second failure time is recorded when a second diagnostic mode detects an uncorrectable error within the NVM cell array using a second set of read voltage levels below and above a normal read voltage level. The first and second failure times are then compared against a threshold wear time value to determine whether or not an imminent read failure is indicated. The diagnostic modes can be run separately for erased NVM cell distributions and programmed NVM cell distributions to provide separate wear rate determinations.
摘要翻译： 公开了基于非易失性存储器（NVM）单元的不可接受的磨损的迫在眉睫的读取故障检测的方法和系统。 在某些实施例中，当第一诊断模式使用低于和高于正常读取电压电平的第一组读取电压电平来检测NVM单元阵列内的不可校正错误时，记录第一故障时间。 当第二诊断模式使用低于和高于正常读取电压电平的第二组读取电压电平来检测NVM单元阵列内的不可校正错误时，记录第二个故障时间。 然后将第一和第二故障时间与阈值磨损时间值进行比较，以确定是否指示即将发生的读取故障。 诊断模式可以单独运行，用于擦除的NVM单元分布和编程的NVM单元分布，以提供单独的磨损率确定。
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公开(公告)号：US09329921B2
公开(公告)日：2016-05-03
申请号：US14262074
申请日：2014-04-25
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/1048 , G11C16/3418 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/50004 , G11C29/52 , G11C2029/0409
摘要： Methods and systems are disclosed for imminent read failure detection using high/low read voltage levels. In certain embodiments, data stored within an array of non-volatile memory (NVM) cells is checked using read voltage levels below and above a normal read voltage level. An imminent read failure is then indicated if errors are detected within the same address for both voltage checks. Further, data stored can be checked using read voltage levels that are incrementally decreased below and incrementally increased above a normal read voltage level. An imminent read failure is then indicated if read errors are detected within the same address for both voltage sweeps and if high/low read voltage levels triggering faults differ by less than a predetermined threshold value. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.
摘要翻译： 公开了使用高/低读取电压电平即将发生的读取故障检测的方法和系统。 在某些实施例中，使用低于和高于正常读取电压电平的读取电压电平来检查存储在非易失性存储器（NVM）单元阵列内的数据。 然后，如果两个电压检查在同一地址内检测到错误，则会显示即将发生的读取失败。 此外，可以使用逐渐减小到低于正常读取电压电平并递增地增加的读取电压电平来检查存储的数据。 然后，如果在两个电压扫描的相同地址内检测到读取错误，并且触发故障的高/低读取电压电平差异小于预定阈值，则会立即指示即将发生的读取失败。 可以使用地址排序器，纠错码（ECC）逻辑和偏置发生器来实现即将发生的故障检测。
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8.发明申请Imminent Read Failure Detection Based Upon Changes In Error Voltage Windows For NVM Cells 有权基于NVM单元的错误电压窗口中的更改即将发生读取故障检测公开(公告)号：US20150309858A1
公开(公告)日：2015-10-29
申请号：US14262157
申请日：2014-04-25
CPC分类号： G06F11/1008 , G06F11/008 , G06F11/073 , G06F11/0757 , G06F11/1068 , G11C11/5642 , G11C16/349 , G11C29/42
摘要： Methods and systems are disclosed for imminent read failure detection based upon changes in error voltage windows for non-volatile memory (NVM) cells. In certain embodiments, data stored within an array of NVM cells is checked at a first time using a diagnostic mode and high/low read voltage sweeps to determine a first error voltage window where high/low uncorrectable errors are detected. Stored data is then checked at a second time using the diagnostic mode and high/low read voltage sweeps to determine a second error voltage window where high/low uncorrectable errors are detected. The difference between the error voltage windows are then compared against a voltage difference threshold value to determine whether or not to indicate an imminent read failure condition. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.
摘要翻译： 公开了基于非易失性存储器（NVM）单元的误差电压窗口的变化的迫在眉睫的读取故障检测的方法和系统。 在某些实施例中，使用诊断模式和高/低读取电压扫描在第一时间检查存储在NVM单元阵列内的数据，以确定检测到高/低不可校正错误的第一误差电压窗口。 然后使用诊断模式和高/低读取电压扫描第二次检查存储的数据，以确定检测到高/低不可校正错误的第二误差电压窗口。 然后将误差电压窗口之间的差异与电压差阈值进行比较，以确定是否指示即将发生的读取故障状况。 可以使用地址排序器，纠错码（ECC）逻辑和偏置发生器来实现即将发生的故障检测。
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公开(公告)号：US20150309856A1
公开(公告)日：2015-10-29
申请号：US14262074
申请日：2014-04-25
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/1048 , G11C16/3418 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/50004 , G11C29/52 , G11C2029/0409
摘要： Methods and systems are disclosed for imminent read failure detection using high/low read voltage levels. In certain embodiments, data stored within an array of non-volatile memory (NVM) cells is checked using read voltage levels below and above a normal read voltage level. An imminent read failure is then indicated if errors are detected within the same address for both voltage checks. Further, data stored can be checked using read voltage levels that are incrementally decreased below and incrementally increased above a normal read voltage level. An imminent read failure is then indicated if read errors are detected within the same address for both voltage sweeps and if high/low read voltage levels triggering faults differ by less than a predetermined threshold value. An address sequencer, error correction code (ECC) logic, and a bias generator can be used to implement the imminent failure detection.
摘要翻译： 公开了使用高/低读取电压电平即将发生的读取故障检测的方法和系统。 在某些实施例中，使用低于和高于正常读取电压电平的读取电压电平来检查存储在非易失性存储器（NVM）单元阵列内的数据。 然后，如果两个电压检查在同一地址内检测到错误，则会显示即将发生的读取失败。 此外，可以使用逐渐减小到低于正常读取电压电平并递增地增加的读取电压电平来检查存储的数据。 然后，如果在两个电压扫描的相同地址内检测到读取错误，并且触发故障的高/低读取电压电平差异小于预定阈值，则会立即指示即将发生的读取失败。 可以使用地址排序器，纠错码（ECC）逻辑和偏置发生器来实现即将发生的故障检测。
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