公开(公告)号：US20110199850A1

公开(公告)日：2011-08-18

申请号：US12706099

申请日：2010-02-16

Applicant: Chen-Lin YANG

Inventor： Chen-Lin YANG

IPC: G11C5/14

CPC classification number: G11C7/08

Abstract: A memory includes a memory cell coupled to a data line. A sense amplifier is coupled to the data line. A power supply node has a first voltage. The first voltage is provided to the sense amplifier. A charge pump circuit is coupled to the sense amplifier. The charge pump circuit is configured to provide a second voltage to the sense amplifier when a read operation is performed.

Abstract translation: 存储器包括耦合到数据线的存储单元。 读出放大器耦合到数据线。 电源节点具有第一电压。 第一电压被提供给读出放大器。 电荷泵电路耦合到读出放大器。 电荷泵电路被配置为当执行读取操作时向读出放大器提供第二电压。

公开(公告)号：US20110055783A1

公开(公告)日：2011-03-03

申请号：US12683599

申请日：2010-01-07

Applicant: Chen-Lin YANG

Inventor： Chen-Lin YANG

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  H01L27/112 ,  H01L27/11226

Abstract: A method includes receiving instructions for designing a ROM array, generating netlists for the ROM array, generating a data file representing a physical layout of the ROM array on a semiconductor wafer, and storing the data file in a computer readable storage medium. The instructions for the ROM array define a layout for a first unit including a first bit cell coupled to a first word line, a bus that may be coupled and uncoupled to a first power supply having a first voltage level, a layout for a second unit coupled to a second word line, and a layout for a third unit having an isolation device and being configured to share a bit line contact with the second unit or another third unit. The layout for the second unit is configured to be arranged at an edge of the ROM array and includes a dummy device.

Abstract translation: 一种方法包括接收用于设计ROM阵列的指令，为ROM阵列生成网表，生成表示半导体晶片上的ROM阵列的物理布局的数据文件，以及将数据文件存储在计算机可读存储介质中。 ROM阵列的指令定义了第一单元的布局，该第一单元包括耦合到第一字线的第一位单元，可以耦合并分离到具有第一电压电平的第一电源的总线，用于第二单元的布局 耦合到第二字线，以及具有隔离装置的第三单元的布局，并且被配置为与第二单元或另一第三单元共享位线接触。 第二单元的布局被配置为布置在ROM阵列的边缘并且包括虚设装置。

公开(公告)号：US20140036580A1

公开(公告)日：2014-02-06

申请号：US13563571

申请日：2012-07-31

Applicant: Chen-Lin YANG ,  Kao-Cheng LIN ,  Chung-Hsien HUA

Inventor： Chen-Lin YANG ,  Kao-Cheng LIN ,  Chung-Hsien HUA

IPC: G11C11/00

CPC classification number: G11C7/04 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C11/413

Abstract: A memory circuit is provided. The memory circuit includes a memory array having a bit line (BL), and a memory cell coupled to the BL; a sense amplifier (SA) coupled to the BL; a tracking bit line (TRKBL); and a comparator coupled to the TRKBL and configured to receive a reference voltage, and to output a strobe signal to the SA.

Abstract translation: 提供存储器电路。 存储器电路包括具有位线（BL）的存储器阵列和耦合到BL的存储器单元; 耦合到所述BL的读出放大器（SA）; 跟踪位线（TRKBL）; 以及耦合到TRKBL并被配置为接收参考电压并且将选通信号输出到SA的比较器。

公开(公告)号：US20120110530A1

公开(公告)日：2012-05-03

申请号：US12913949

申请日：2010-10-28

Applicant: Chen-Lin YANG ,  Wei Min CHAN

Inventor： Chen-Lin YANG ,  Wei Min CHAN

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5068

Abstract: The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated.

Abstract translation: 本申请公开了根据电路设计制备用于制造集成电路芯片的布局的方法。 在至少一个实施例中，生成用于基于电路设计的布局的图案。 在生成图案之后，确定在布局中是否违反了至少一个布局规则，根据预定的最大值来指定至少一个布局规则，用于沿着信号路径的估计电压降中的至少一个 信号路径上的布局或估计的电流密度。 如果违反了至少一个布局规则，则会显示违规。