公开(公告)号：US20120212866A1

公开(公告)日：2012-08-23

申请号：US13029706

申请日：2011-02-17

申请人： Chen-Ting KO ,  Jinn-Yeh CHIEN

发明人： Chen-Ting KO ,  Jinn-Yeh CHIEN

IPC分类号： H02H9/04

CPC分类号： H03K19/018521 ,  H03K17/102

摘要： An output driver having a power supply line, a control switch, at least one protection device and at least one voltage clamp device. The control switch disposed between the at least one protection device and the power supply line an output line. The at least one protection device disposed in a series arrangement between the output line and the control switch. The at least one voltage clamp device disposed across a corresponding protection device and adapted to clamp a voltage across the protection device below a predetermined threshold voltage.

摘要翻译： 具有电源线，控制开关，至少一个保护装置和至少一个电压钳位装置的输出驱动器。 所述控制开关设置在所述至少一个保护装置和所述电源线之间的输出线路。 所述至少一个保护装置以输出线和控制开关之间的串联布置设置。 所述至少一个电压钳位装置跨越相应的保护装置设置并且适于将跨过保护装置的电压钳位在预定阈值电压以下。

公开(公告)号：US20120169361A1

公开(公告)日：2012-07-05

申请号：US12981618

申请日：2010-12-30

申请人： Jinn-Yeh CHIEN ,  Hao-Jie Zhan

发明人： Jinn-Yeh CHIEN ,  Hao-Jie Zhan

IPC分类号： G01R31/3187

CPC分类号： G01R31/31716

摘要： An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.

摘要翻译： 集成电路（IC），包括IC基板上的接收器。 接收器被配置为接收受压输入信号。 在IC基板上提供内置自检（BIST）电路，用于测试接收器。 BIST电路包括编码器，其被配置为接收输入信号并且识别是否存在第一条件，其中两个或更多个连续的输入数据位具有彼此相同的极性。 输出驱动器电路提供对应于两个或更多个连续输入数据位的应力输入信号。 当编码器识别出两个或多个连续的输入数据位彼此具有不同的极性时，编码器识别出第一个条件存在时，应力输入信号具有较大的幅度。

公开(公告)号：US20120280718A1

公开(公告)日：2012-11-08

申请号：US13551331

申请日：2012-07-17

申请人： Shu-Chun YANG ,  Jinn-Yeh CHIEN

发明人： Shu-Chun YANG ,  Jinn-Yeh CHIEN

IPC分类号： H03K5/22

CPC分类号： H03K5/1534 ,  H04L7/0012

摘要： This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering.

摘要翻译： 该描述涉及一种边缘检测器，其包括脉冲发生器，其被配置为当第一时钟和第二时钟处于相同的逻辑电平时产生第一脉冲，并且当第一时钟和第二时钟处于不同的逻辑电平时产生第二脉冲。 边缘检测器还包括配置为对第一脉冲充电的第一RC电路和被配置为对第二脉冲充电的第二RC电路。 边缘检测器还包括基于第一脉冲或第二脉冲的宽度被配置为提供选择信号以选择用于触发的第二时钟的边沿的电路。