公开(公告)号：US20120187484A1

公开(公告)日：2012-07-26

申请号：US13216963

申请日：2011-08-24

申请人： Cheol-Ho CHO ,  Choul-Joo Ko

发明人： Cheol-Ho CHO ,  Choul-Joo Ko

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0873 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/7835

摘要： A lateral double diffused metal oxide semiconductor (LDMOS) device includes a first buried layer having a second conduction type formed in an epitaxial layer having a first conduction type, a first high-voltage well having the second conduction type formed above one region of the first buried layer, a first drain diffusion region having the first conduction type formed above another region of the first buried layer, a second drain diffusion region having the second conduction type formed in a partial region of the first drain diffusion region, the second drain diffusion region including a gate pattern and a drain region, and a first body having the first conduction type including a source region and having a surface in contact with the second drain diffusion region.

摘要翻译： 横向双扩散金属氧化物半导体（LDMOS）器件包括具有形成在具有第一导电类型的外延层中的第二导电类型的第一掩埋层，具有第二导电类型的第一高电压阱形成在第一 第一漏极扩散区，形成在第一掩埋层的另一区域上方的具有第一导电类型的第一漏极扩散区域，形成在第一漏极扩散区域的部分区域中的具有第二导电类型的第二漏极扩散区域，第二漏极扩散区域 包括栅极图案和漏极区域，以及具有包括源极区域并且具有与第二漏极扩散区域接触的表面的第一导电类型的第一主体。

公开(公告)号：US20090166763A1

公开(公告)日：2009-07-02

申请号：US12248141

申请日：2008-10-09

申请人： Choul-Joo Ko

发明人： Choul-Joo Ko

IPC分类号： H01L47/00 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/66696

摘要： Embodiments relate to a semiconductor device having a minimized on-resistance. According to embodiments, a semiconductor device may include at least one of the following: a first conductive type well formed on and/or over a semiconductor substrate, a second conductive type body region formed within the first conductive type well a first conductive type source region formed on and/or over the surface of the body region, a first conductive type drain region formed on and/or over the surface of the first conductive type well. Further, according to embodiments, a semiconductor device may include a field insulation layer positioned between the first conductive type source region and the first conductive type drain region and a gate electrode formed on and/or over the field insulation layer. The source region may be formed at a lower position than the drain region.

摘要翻译： 实施例涉及具有最小导通电阻的半导体器件。 根据实施例，半导体器件可以包括以下中的至少一个：在半导体衬底上和/或之上形成的第一导电类型阱，形成在第一导电类型阱内的第二导电类型体区域，第一导电类型源极区域 形成在主体区域的表面上和/或上方，形成在第一导电类型孔的表面上和/或上方的第一导电类型漏极区域。 此外，根据实施例，半导体器件可以包括位于第一导电型源极区域和第一导电型漏极区域之间的场绝缘层以及形成在场绝缘层上和/或上部的栅电极。 源极区域可以形成在比漏极区域更低的位置处。

公开(公告)号：US20090001461A1

公开(公告)日：2009-01-01

申请号：US12141961

申请日：2008-06-19

申请人： Choul-Joo Ko

发明人： Choul-Joo Ko

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0878 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： An LDMOS device and a method for fabricating the same that may include a first conductivity-type semiconductor substrate having an active area and a field area; a second conductivity-type deep well formed on the first conductivity-type semiconductor substrate; a second conductivity-type adjusting layer located in the second conductivity-type deep well; a first conductivity-type body formed in the second conductivity-type deep well; an insulating layer formed on the first conductivity-type semiconductor substrate in the active area and the field area; a gate area formed on the first conductivity-type semiconductor substrate in the active area; a second conductivity-type source area formed in the first conductivity-type body; a second conductivity-type drain area formed in the second conductivity-type deep well. Accordingly, such an LDMOS device has a high breakdown voltage without an increase in on-resistance.

摘要翻译： 一种LDMOS器件及其制造方法，其可以包括具有有源区和场区的第一导电型半导体衬底; 在第一导电型半导体衬底上形成的第二导电型深阱; 位于第二导电型深井中的第二导电型调节层; 形成在第二导电型深井中的第一导电型体; 形成在所述有源区域和所述场区域中的所述第一导电型半导体基板上的绝缘层; 形成在所述有源区域中的所述第一导电型半导体基板上的栅极区域; 形成在第一导电型体中的第二导电型源区; 在第二导电型深井中形成的第二导电型漏极区。 因此，这种LDMOS器件具有高的击穿电压而不增加导通电阻。

公开(公告)号：US08089124B2

公开(公告)日：2012-01-03

申请号：US12141961

申请日：2008-06-19

申请人： Choul-Joo Ko

发明人： Choul-Joo Ko

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/0878 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： An LDMOS device and a method for fabricating the same that may include a first conductivity-type semiconductor substrate having an active area and a field area; a second conductivity-type deep well formed on the first conductivity-type semiconductor substrate; a second conductivity-type adjusting layer located in the second conductivity-type deep well; a first conductivity-type body formed in the second conductivity-type deep well; an insulating layer formed on the first conductivity-type semiconductor substrate in the active area and the field area; a gate area formed on the first conductivity-type semiconductor substrate in the active area; a second conductivity-type source area formed in the first conductivity-type body; a second conductivity-type drain area formed in the second conductivity-type deep well. Accordingly, such an LDMOS device has a high breakdown voltage without an increase in on-resistance.

摘要翻译： 一种LDMOS器件及其制造方法，其可以包括具有有源区和场区的第一导电型半导体衬底; 在第一导电型半导体衬底上形成的第二导电型深阱; 位于第二导电型深井中的第二导电型调节层; 形成在第二导电型深井中的第一导电型体; 形成在所述有源区域和所述场区域中的所述第一导电型半导体基板上的绝缘层; 形成在所述有源区域中的所述第一导电型半导体基板上的栅极区域; 形成在第一导电型体中的第二导电型源区; 在第二导电型深井中形成的第二导电型漏极区。 因此，这种LDMOS器件具有高的击穿电压而不增加导通电阻。

公开(公告)号：US07944002B2

公开(公告)日：2011-05-17

申请号：US12248141

申请日：2008-10-09

申请人： Choul-Joo Ko

发明人： Choul-Joo Ko

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/66696

摘要： Embodiments relate to a semiconductor device having a minimized on-resistance. According to embodiments, a semiconductor device may include at least one of the following: a first conductive type well formed on and/or over a semiconductor substrate, a second conductive type body region formed within the first conductive type well a first conductive type source region formed on and/or over the surface of the body region, a first conductive type drain region formed on and/or over the surface of the first conductive type well. Further, according to embodiments, a semiconductor device may include a field insulation layer positioned between the first conductive type source region and the first conductive type drain region and a gate electrode formed on and/or over the field insulation layer. The source region may be formed at a lower position than the drain region.

摘要翻译： 实施例涉及具有最小导通电阻的半导体器件。 根据实施例，半导体器件可以包括以下中的至少一个：在半导体衬底上和/或之上形成的第一导电类型阱，形成在第一导电类型阱内的第二导电类型体区域，第一导电类型源极区域 形成在主体区域的表面上和/或上方，形成在第一导电类型孔的表面上和/或上方的第一导电类型漏极区域。 此外，根据实施例，半导体器件可以包括位于第一导电型源极区域和第一导电型漏极区域之间的场绝缘层以及形成在场绝缘层上和/或上部的栅电极。 源极区域可以形成在比漏极区域更低的位置处。