公开(公告)号：US07199045B2

公开(公告)日：2007-04-03

申请号：US10854061

申请日：2004-05-26

申请人： Chi Wen Liu ,  Jung Chih Tsao ,  Shih Tzung Chang ,  Ying Lang Wang ,  Kei Wei Chen

发明人： Chi Wen Liu ,  Jung Chih Tsao ,  Shih Tzung Chang ,  Ying Lang Wang ,  Kei Wei Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/76877

摘要： A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.

摘要翻译： 在半导体或其他亚微米器件衬底中形成填充金属的开口的方法包括在衬底表面和开口中形成导电体层，其中导电体层具有第一晶粒尺寸。 导电盖层形成在导电体层之上，导电盖层具有基本上小于第一晶粒尺寸的第二晶粒尺寸。 导电体和盖层中的至少一个然后被平坦化以形成基本上与衬底表面重合的平坦表面。

公开(公告)号：US06784077B1

公开(公告)日：2004-08-31

申请号：US10270973

申请日：2002-10-15

申请人： Shih-Chi Lin ,  Chih Chung Lee ,  Guey Bao Huang ,  Szu-An Wu ,  Ying Lang Wang ,  Chun Chun Yeh

发明人： Shih-Chi Lin ,  Chih Chung Lee ,  Guey Bao Huang ,  Szu-An Wu ,  Ying Lang Wang ,  Chun Chun Yeh

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method of forming a silicon oxide, shallow trench isolation (STI) region, featuring a silicon rich, silicon oxide layer used to protect the STI region from a subsequent wet etch procedure, has been developed. The method features depositing a silicon oxide layer via PECVD procedures, without RF bias, using a high silane to oxygen ratio, resulting in a silicon rich, silicon oxide layer, located surrounding the STI region. The low etch rate of the silicon rich, silicon oxide layer, protect the silicon oxide STI region from buffered hydrofluoric wet etch procedures, used for removal of a dioxide pad layer.

摘要翻译： 已经开发了一种形成氧化硅，浅沟槽隔离（STI）区域的方法，其特征在于用于保护STI区域免受后续湿蚀刻过程的富硅氧化硅层。 该方法的特征是通过PECVD方法沉积氧化硅层，无需RF偏压，使用高硅烷与氧气比，导致位于STI区周围的富含硅的氧化硅层。 富硅氧化硅层的低蚀刻速率保护硅氧化物STI区域免受用于去除二氧化物焊盘层的缓冲氢氟酸湿蚀刻工艺。

公开(公告)号：US06586347B1

公开(公告)日：2003-07-01

申请号：US09978229

申请日：2001-10-16

申请人： Chung-Shi Liu ,  Hui-Ling Wang ,  Szu-An Wu ,  Chun-Ching Tsan ,  Ying Lang Wang ,  Tong Hua Kuan

发明人： Chung-Shi Liu ,  Hui-Ling Wang ,  Szu-An Wu ,  Chun-Ching Tsan ,  Ying Lang Wang ,  Tong Hua Kuan

IPC分类号： H01L2131

CPC分类号： H01L21/76801 ,  H01L21/76832

摘要： An improved composite dielectric structure and method of forming thereof which prevents delamination of FSG (F-doped SiO2) and allows FSG to be used as the interlevel dielectric between successive conducting interconnection patterns in multilevel integrated circuit structures has been developed. The composite dielectric structure comprises FSG, undoped silicon oxide (optional), silicon-rich silicon oxide and silicon nitride. The silicon-rich silicon oxide layer having a thickness between about 1000 and 2000 Angstroms prevents reaction of F atoms from the FSG layer with the silicon nitride layer during subsequent manufacturing heat treatment cycles and prevents the deleterious formation of delamination bubbles which cause peeling of the FSG layer.

摘要翻译： 已经开发了一种改进的复合电介质结构及其形成方法，其防止FSG（F掺杂SiO 2）的分层并且允许FSG用作多电平集成电路结构中的连续导电互连图案之间的层间电介质。 复合电介质结构包括FSG，未掺杂的氧化硅（可选），富硅氧化硅和氮化硅。 厚度在约1000和2000埃之间的富含硅的氧化硅层防止了F原子与氮化硅层在随后的制造热处理循环中的反应，并且防止了导致FSG剥离的分层气泡的有害形成 层。