公开(公告)号：US06724036B1

公开(公告)日：2004-04-20

申请号：US09654776

申请日：2000-09-05

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： A stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling is described. An unconventionally high isolation oxide layer is formed in a shallow trench isolation (STI) in a substrate. The deep opening in the space between the STIs is conformally lined with a polysilicon to form a floating gate extending above the opening. A conformal intergate oxide lines the entire floating gate. A layer of polysilicon overlays the intergate oxide and protrudes downward into the openings to form a control gate with increased coupling to the floating gate.

摘要翻译： 描述了具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极闪存单元。 在衬底中的浅沟槽隔离（STI）中形成非常规的高隔离氧化层。 在STI之间的空间中的深开口共形地衬有多晶硅以形成在开口上方延伸的浮动栅极。 保形隔离层氧化物对整个浮动栅线进行排列。 一层多晶硅覆盖了间隔栅极氧化物并向下突出到开口中，以形成一个与浮动栅极增加耦合的控制栅极。

公开(公告)号：US6153494A

公开(公告)日：2000-11-28

申请号：US310257

申请日：1999-05-12

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chrong Jung Lin ,  Jong Chen ,  Hung-Der Su

IPC分类号： H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.

摘要翻译： 提供一种用于形成具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极快闪存储器单元的方法。 这是通过首先沉积非常规高或较厚的氮化物层，然后通过氮化物层形成浅沟槽隔离（STI）到衬底中，用隔离氧化物填充STI，从而除去氮化物，从而留下围绕 填充STI，用第一多晶硅层保形地填充开口以形成浮置栅极，在浮置栅极上形成多晶硅层，然后形成第二多晶硅层以形成控制栅极，并最终形成堆叠的自对准源 本发明的闪存单元。 还提供了堆叠栅极闪存单元，其具有具有高阶氧化物和高横向耦合的浅沟槽隔离。

公开(公告)号：US07417278B2

公开(公告)日：2008-08-26

申请号：US11122726

申请日：2005-05-05

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

摘要翻译： 提供具有能够与电池的浮动栅极三维耦合的三维源的分裂栅极闪存单元及其形成方法。 这是通过首先形成隔离沟槽，用共形氧化物衬里，然后用隔离氧化物填充，然后对其进行蚀刻，以在沟槽的上部形成三维耦合区域。 接下来通过用多晶硅填充沟槽的三维区域并对其进行蚀刻来形成浮栅。 控制栅极通过中间多晶硅氧化物形成在浮动栅上。 浮栅形成延伸到沟槽的三维耦合区域中的支腿，从而提供与源也呈三维区域的三维耦合。 形成第三维的浮动栅的腿或侧壁提供了增加源极和浮动栅极之间的耦合的额外区域。 以这种方式，在不增加电池尺寸的同时实现更高的耦合比，同时通过沿着侧壁共享栅极电压来减轻源极区域的穿通和结断流。

公开(公告)号：US06573555B1

公开(公告)日：2003-06-03

申请号：US09587464

申请日：2000-06-05

申请人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

发明人： Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Chia-Ta Hsieh

IPC分类号： H01L29788

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a concave top surface which intersects with the sidewalls to form a sharp edge. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The sharp edge at the intersection of the concave top surface and the sidewalls of the floating gate produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate. The P-channel flash memory cell has a higher impact ionization rage for creating hot electrons so that the distance between the source and drain junctions and the length of the floating gate can be kept small thereby permitting the dimensions of the flash memory cell to be shrunk.

摘要翻译： 分裂门P沟道快闪存储单元以及形成分离栅极P沟道闪存单元的方法，其避免高擦除电压，编程期间的反向隧穿，漏极干扰和过度擦除问题，并且允许缩小单元尺寸。 控制门具有与侧壁相交以形成锋利边缘的凹顶表面。 通过从通道进入浮动栅极的热电子注入，用电子对浮动栅极充电来对单元进行编程。 使用Fowler-Nordheim隧道将多余的电子从浮动栅极放电到控制栅中来消除电池。 在凹顶表面和浮动栅极的相交处的尖锐边缘在控制栅极和浮动栅极之间产生高电场，以在浮动栅极和控制栅极之间仅具有适度的电压差来实现Fowler-Nordheim隧道 。 P沟道闪速存储单元对于产生热电子具有较高的冲击电离强度，使得源极和漏极结之间的距离和浮置栅极的长度可以保持较小，从而允许闪存单元的尺寸缩小 。

公开(公告)号：US06538277B2

公开(公告)日：2003-03-25

申请号：US09920601

申请日：2001-08-02

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.

摘要翻译： 公开了一种形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多尖端）的新方法。 在不使用厚多晶硅层作为浮动栅极的情况下形成多尖端。 这可以通过在多晶硅上形成氧化层并氧化多晶硅的侧壁来实现。 由于浮栅的多晶硅的起始厚度相对较薄，所以形成的栅极尖或多尖端也必然是薄且尖锐的。 因此，该方法避免了超大规模集成技术的缩小设备中遇到的氧化物薄化问题，提高了EEPROM的快速可编程性和擦除性能。

公开(公告)号：US06534821B2

公开(公告)日：2003-03-18

申请号：US09927071

申请日：2001-08-10

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.

公开(公告)号：US06465841B1

公开(公告)日：2002-10-15

申请号：US09709589

申请日：2000-11-13

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  H01L29/42324

摘要： A method is disclosed to form a split-gate flash memory cell having nitride spacers formed on a pad oxide and prior the forming of an inter-poly oxide layer thereover. In this manner, any damage that would normally occur to the inter-poly oxide during the etching of the nitride spacers subsequent to the forming of the inter-poly oxide is avoided. Consequently, the variation in the thickness of the inter-poly oxide due to the unpredictable damage to the underlying spacers is also avoided by reversing the order in which the spacers and the inter-poly oxide are formed, including the forming of the pad oxide first. As a result, variation in the erase speed of the inter-gate flash memory cell is prevented, both for cells fabricated on the same wafer as well as on different wafers on same or different production lines.

摘要翻译： 公开了一种形成具有形成在衬垫氧化物上的氮化物间隔物并且之前形成多晶氧化物层的分裂栅极快闪存储器单元的方法。 以这种方式，避免了在形成多晶硅氧化物之前在氮化物间隔物的蚀刻期间多晶氧化物通常会发生的任何损伤。 因此，通过反转形成间隔物和多晶氧化物的顺序，包括首先形成衬垫氧化物，也可以避免由于对下面的间隔物的不可预测的损伤而导致的多晶氧化物厚度的变化 。 结果，对于在同一晶片上以及相同或不同生产线上的不同晶片上制造的单元，都能够防止栅极间闪存单元的擦除速度的变化。

公开(公告)号：US06380583B1

公开(公告)日：2002-04-30

申请号：US09679512

申请日：2000-10-06

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.

摘要翻译： 提供具有能够与电池的浮动栅极三维耦合的三维源的分裂栅极闪存单元及其形成方法。 这是通过首先形成隔离沟槽，用共形氧化物衬里，然后用隔离氧化物填充，然后对其进行蚀刻，以在沟槽的上部形成三维耦合区域。 接下来通过用多晶硅填充沟槽的三维区域并对其进行蚀刻来形成浮栅。 控制栅极通过中间多晶硅氧化物形成在浮动栅上。 浮栅形成延伸到沟槽的三维耦合区域中的支腿，从而提供与源也呈三维区域的三维耦合。 形成第三维的浮动栅的腿或侧壁提供了增加源极和浮动栅极之间的耦合的额外区域。 以这种方式，在不增加电池尺寸的同时实现更高的耦合比，同时通过沿着侧壁共享栅极电压来减轻源极区域的穿通和结断流。

公开(公告)号：US06333228B1

公开(公告)日：2001-12-25

申请号：US09534160

申请日：2000-03-24

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided to improve the control of bird's beak profile of poly in a split gate flash memory cell. The control of the bird's beak profile is achieved in a first embodiment where the polycrystalline layer of the floating gate is annealed at a high temperature. The annealing promotes small grain size and hence smoother surface in the polysilicon, which in turn promotes sharper poly tip. The smoother poly surface also results in thinner inter-poly between the floating gate and the control gate, which together with the sharp poly tip, enhances the erase speed of the split-gate flash memory cell. In a second embodiment, the performance is further enhanced by providing an amorphous silicon for the floating gate, because the amorphous nature of the silicon yields a very smooth surface. This smooth surface is transferred to the recrystallized state of the silicon layer through annealing. Thus, a good control for the bird's beak is achieved. A sharp and short poly tip then results from a well controlled and well-defined bird's beak. Hence, an enhanced split-gate flash memory cell follows.

摘要翻译： 提供了一种方法来改善分裂门闪存单元中聚鸟的鸟嘴形状的控制。 在第一实施例中实现鸟嘴形状的控制，其中浮栅的多晶层在高温下退火。 退火促进了多晶硅中的小晶粒尺寸和因此更平滑的表面，这又促进了更尖锐的多晶硅尖端。 更平滑的多晶面也导致浮栅和控制栅之间的更薄的多晶硅，其与尖锐的多晶硅尖端一起增强了分离栅闪存单元的擦除速度。 在第二实施例中，通过为浮置栅极提供非晶硅来进一步提高性能，因为硅的无定形性能产生非常光滑的表面。 该光滑表面通过退火转移到硅层的再结晶状态。 因此，可以很好地控制鸟的喙。 然后，一个尖锐和短的多头尖端来自良好控制和明确定义的鸟的喙。 因此，增强的分闸式闪存单元如下。

公开(公告)号：US06188103B1

公开(公告)日：2001-02-13

申请号：US09196600

申请日：1998-11-20

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory cell. This is accomplished by implanting nitrogen ions in the first polysilicon layer of the cell and removing them from the area where the floating gate is to be formed. Then, when the polysilicon layer is oxidized to form polyoxide, the floating gate region without the nitrogen ions oxidizes faster than the surrounding area still having the nitrogen ions. Consequently, the bird's beak that is formed at the edges of the polyoxide assumes a sharper shape with smaller size than that is found in prior art. This results in an increase in the erase speed of the memory cell.

摘要翻译： 提供了一种用于形成短而尖锐的门鸟喙的方法，以便增加分闸式闪存单元的擦除速度。 这是通过在电池的第一多晶硅层中注入氮离子并将其从要形成浮栅的区域中去除来实现的。 然后，当多晶硅层被氧化形成聚氧化物时，没有氮离子的浮栅区域比仍然具有氮离子的周围区域更快地氧化。 因此，形成在多氧化物边缘的鸟嘴形状比现有技术中发现的具有更小的形状。 这导致存储单元的擦除速度的增加。