公开(公告)号：US06538277B2

公开(公告)日：2003-03-25

申请号：US09920601

申请日：2001-08-02

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.

摘要翻译： 公开了一种形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多尖端）的新方法。 在不使用厚多晶硅层作为浮动栅极的情况下形成多尖端。 这可以通过在多晶硅上形成氧化层并氧化多晶硅的侧壁来实现。 由于浮栅的多晶硅的起始厚度相对较薄，所以形成的栅极尖或多尖端也必然是薄且尖锐的。 因此，该方法避免了超大规模集成技术的缩小设备中遇到的氧化物薄化问题，提高了EEPROM的快速可编程性和擦除性能。

公开(公告)号：US06534821B2

公开(公告)日：2003-03-18

申请号：US09927071

申请日：2001-08-10

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.

公开(公告)号：US06312989B1

公开(公告)日：2001-11-06

申请号：US09489496

申请日：2000-01-21

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.

摘要翻译： 公开了一种用于形成具有突出源的分裂栅极闪存单元来代替常规扁平源的方法。 垂直突出的源结构具有顶部和底部。 底部是多晶硅，而顶部是多晶氧化物。 源极上的突出结构的垂直壁用于形成具有中间栅极氧化物的垂直浮动栅极和间隔物控制栅极。 因为现在通过垂直壁提供源极和浮动栅极之间的耦合，所以耦合面积比常规扁平源大得多。 此外，不再存在源极和漏极之间的电压穿通的问题。 垂直浮动栅极也变薄，使得所得到的薄而尖锐的多尖端进一步增强了闪存单元的擦除和编程速度。 源结构和浮置栅极的垂直取向以及间隔物控制栅极与浮置栅极的自对准一起使得可以基本上减小存储单元。

公开(公告)号：US06309928B1

公开(公告)日：2001-10-30

申请号：US09208913

申请日：1998-12-10

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F—N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.

摘要翻译： 公开了一种形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多尖端）的新方法。 在不使用厚多晶硅层作为浮动栅极的情况下形成多尖端。 这可以通过在多晶硅上形成氧化层并氧化多晶硅的侧壁来实现。 由于浮栅的多晶硅的起始厚度相对较薄，所以形成的栅极尖或多尖端也必然是薄且尖锐的。 因此，该方法避免了超大规模集成技术的缩小设备中遇到的氧化物薄化问题，提高了EEPROM的快速可编程性和擦除性能。

公开(公告)号：US6046086A

公开(公告)日：2000-04-04

申请号：US100691

申请日：1998-06-19

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  Y10S438/981

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split-gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the floating gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.

摘要翻译： 提供了一种用于形成具有减小的尺寸，增加的电容耦合和改进的数据保持能力的分离栅极闪存单元的方法。 分离栅极单元还在衬底和浮置栅极之间以及浮置栅极和控制栅极之间提供适当的栅极氧化物厚度，以及在主栅极氧化物层上明智地形成的额外的薄的氮化物层，以克服问题 的浮动栅极的低数据保持容量和现有技术的浮动栅极和源极之间的减小的电容耦合。

公开(公告)号：US06326660B1

公开(公告)日：2001-12-04

申请号：US09524522

申请日：2000-03-13

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  Y10S438/981

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the float gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.

摘要翻译： 提供了一种用于形成具有减小的尺寸，增加的电容耦合和改进的数据保持能力的分离栅极闪存单元的方法。 分离栅极单元还在衬底和浮动栅极之间以及浮动栅极和控制栅极之间提供适当的栅极氧化物厚度以及在主栅极氧化物层上明智地形成的额外的薄的氮化物层，以克服以下问题： 浮动栅极的低数据保持容量和浮动栅极与现有技术的源之间的减小的电容耦合。

公开(公告)号：US06171906B2

公开(公告)日：2001-01-09

申请号：US09379227

申请日：1999-08-23

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a sharp beak of poly which substantially improves the programming erase speed of the cell. The sharp beak is formed through an extra and judicious wet etch of the polyoxide formed after the oxidation of the first polysilicon layer. The extra oxide dip causes the polyoxide to be removed peripherally thus forming a re-entrant cavity along the edge of the floating gate. The re-entrant beak is such that it does not get damaged during the subsequent process steps and is especially suited for cell sizes smaller than 0.35 micrometers.

摘要翻译： 提供了一种用于形成具有尖锐尖峰的分裂栅极闪存单元的方法，其大大改善了单元的编程擦除速度。 通过对第一多晶硅层的氧化后形成的多氧化物进行额外且明智的湿法蚀刻，形成尖锐的喙。 额外的氧化物浸渍导致周围地去除多氧化物，从而沿着浮动栅极的边缘形成重入腔。 再入口的喙使得在后续工艺步骤中不会损坏，特别适用于小于0.35微米的电池尺寸。

公开(公告)号：US5879992A

公开(公告)日：1999-03-09

申请号：US115719

申请日：1998-07-15

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/8427

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.

摘要翻译： 提供了一种用于形成分支栅极快闪存储器单元的方法，其具有支撑不同厚度的多晶硅氧化物的台阶聚合物，以改善电池的全部性能。 多晶氧化物形成在第一多晶硅层的部分上，该第一多晶硅层又被部分蚀刻以形成邻近聚氧化物下面的浮动栅极的侧壁的台阶。 接着在步骤poly上由热的温度氧化物形成间隔物。 然后形成间极氧氮化物，并且控制栅极被图案化与浮置栅极与介入的多晶硅氧化物重叠。 步进多晶硅和间隔件在控制栅极和浮动栅极之间形成适当的距离，同时保持多晶硅尖端和控制栅极之间的距离不变，使得控制栅极和浮动栅极之间以及浮动栅极和浮动栅极之间的适当耦合 实现了衬底，从而改进了具有阶梯聚光的分离栅极闪存的全部性能。

公开(公告)号：US06229176B1

公开(公告)日：2001-05-08

申请号：US09257833

申请日：1999-02-25

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L2976

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.

摘要翻译： 提供了一种用于形成分支栅极快闪存储器单元的方法，其具有支撑不同厚度的多晶硅氧化物的台阶聚合物，以改善电池的全部性能。 多晶氧化物形成在第一多晶硅层的部分上，该第一多晶硅层又被部分蚀刻以形成邻近聚氧化物下面的浮动栅极的侧壁的台阶。 接着在步骤poly上由热的温度氧化物形成间隔物。 然后形成间极氧氮化物，并且控制栅极被图案化与浮置栅极与介入的多晶硅氧化物重叠。 步进多晶硅和间隔件在控制栅极和浮动栅极之间形成适当的距离，同时保持多晶硅尖端和控制栅极之间的距离不变，使得控制栅极和浮动栅极之间以及浮动栅极和浮动栅极之间的适当耦合 实现了衬底，从而改进了具有阶梯聚光的分离栅极闪存的全部性能。

公开(公告)号：US5970371A

公开(公告)日：1999-10-19

申请号：US110418

申请日：1998-07-06

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L21/336 ,  H01L29/423

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a sharp beak of poly which substantially improves the programming erase speed of the cell. The sharp beak is formed through an extra and judicious wet etch of the polyoxide formed after the oxidation of the first polysilicon layer. The extra oxide dip causes the polyoxide to be removed peripherally thus forming a re-entrant cavity along the edge of the floating gate. The re-entrant beak is such that it does not get damaged during the subsequent process steps and is especially suited for cell sizes smaller than 0.35 micrometers.

摘要翻译： 提供了一种用于形成具有尖锐尖峰的分裂栅极闪存单元的方法，其大大改善了单元的编程擦除速度。 通过对第一多晶硅层的氧化后形成的多氧化物进行额外且明智的湿法蚀刻，形成尖锐的喙。 额外的氧化物浸渍导致周围地去除多氧化物，从而沿着浮动栅极的边缘形成重入腔。 再入口的喙使得在后续工艺步骤中不会损坏，特别适用于小于0.35微米的电池尺寸。