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1.发明授权Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip 有权专用于可编程存储器架构和芯片上互连网络的方法和装置公开(公告)号：US07185309B1
公开(公告)日：2007-02-27
申请号：US10769591
申请日：2004-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.
摘要翻译： 描述了用于实现使用集成电路的消息处理系统的可编程架构。 在一个示例中，接收包括存储器系统的属性的规范数据。 响应于规范数据生成存储器系统的逻辑描述。 逻辑描述定义了存储器组件和存储器互连组件。 响应于逻辑描述生成存储器系统的物理描述。 物理描述包括与由存储器组件定义的集成电路相关联的存储器电路。 存储器电路包括由存储器互连部件定义的互连拓扑。
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2.发明授权Memory apparatus for a message processing system and method of providing same 有权用于消息处理系统的存储装置及其提供方法公开(公告)号：US07281093B1
公开(公告)日：2007-10-09
申请号：US11019484
申请日：2004-12-21
IPC分类号： G06F13/00
CPC分类号： G06F13/1657
摘要： Memory apparatus for a message processing system and method of providing the same is described. In one example, a message processing system (200) includes a set of n processing elements (202) for processing messages, where n is an integer greater than zero. A set of m memories (204) is provided for storing the messages, where m is an integer greater than zero. Multiplexing logic (206) is provided for coupling each of the processing elements to each of the memories. Control logic (208) is provided for driving the multiplexing logic to provide access to each of the memories among the processing elements in accordance with a gated module-n schedule.
摘要翻译： 描述了用于消息处理系统的存储装置及其提供方法。 在一个示例中，消息处理系统（200）包括用于处理消息的一组n个处理元件（202），其中n是大于零的整数。 提供一组m个存储器（204）用于存储消息，其中m是大于零的整数。 多路复用逻辑（206）被提供用于将每个处理元件耦合到每个存储器。 控制逻辑（208）被提供用于驱动多路复用逻辑，以根据门控模块n调度来提供对处理元件中每个存储器的访问。
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公开(公告)号：US08065130B1
公开(公告)日：2011-11-22
申请号：US12465247
申请日：2009-05-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H04L45/60
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.
摘要翻译： 描述了用于实现使用集成电路的消息处理系统的可编程架构。 在一个示例中，集成电路的可配置逻辑被配置为具有多个线程电路和存储器。 消息被接收到集成电路以存储在存储器中。 利用多个线程来访问存储器以同时处理多个消息。
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公开(公告)号：US07784014B1
公开(公告)日：2010-08-24
申请号：US11799897
申请日：2007-05-03
申请人： Gordon J. Brebner , Christopher E. Neely , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni , Michael A. Baxter , Henry E. Styles , Graham F. Schelle
发明人： Gordon J. Brebner , Christopher E. Neely , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni , Michael A. Baxter , Henry E. Styles , Graham F. Schelle
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.
摘要翻译： 提供了一种从处理器对网络分组的处理的文本语言规范生成网络分组处理器的硬件描述语言（HDL）规范的方法。 处理器包括前视级，操作级，插入/移除级和交错级。 文本语言规范识别处理器的端口。 文本语言规范包括进出网络数据包的类型或类型的格式。 每个格式包括网络包类型的字段。 文本语言规范包括每个输入端口和在输入端口接收的每种类型的传入网络分组的过程。 每个过程包括用于根据状态数据和/或网络分组类型的字段修改网络分组类型的字段的一个或多个动作。
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5.发明授权Micro-coded processors for concurrent processing in a programmable logic device 有权用于可编程逻辑器件中并发处理的微编码处理器公开(公告)号：US07398502B1
公开(公告)日：2008-07-08
申请号：US11299976
申请日：2005-12-12
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H01L27/118
摘要： A method and system for concurrent data processing, and an integrated circuit having programmable logic therefor, are described. A multi-threaded application is parsed into respective threads. Data value variables, data operators, data processing order of execution, and data result variables are identified from the threads. A code listing is generated associated with each of the threads for the data value variables, the data operators, the data processing order of execution, and the data result variables identified. Source and destination address information is associated with the data value variables and the data result variables. The source and destination address information is ordered to preserve the data processing order of execution. A configuration bitstream is generated for instantiating thread-specific processors in programmable logic, the thread-specific processors associated with the threads each having at least a portion of the data operators.
摘要翻译： 描述了用于并行数据处理的方法和系统以及具有可编程逻辑的集成电路。 多线程应用程序被分析到相应的线程中。 从线程中识别出数据值变量，数据运算符，数据处理执行顺序和数据结果变量。 生成与数据值变量，数据运算符，数据处理执行顺序和识别的数据结果变量的每个线程相关联的代码列表。 源和目标地址信息与数据值变量和数据结果变量相关联。 源地址和目标地址信息被排序以保持执行的数据处理顺序。 生成用于在可编程逻辑中实例化线程特定处理器的配置比特流，所述线程专用处理器与每个具有至少一部分数据运算符的线程相关联。
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6.发明授权公开(公告)号：US07770179B1
公开(公告)日：2010-08-03
申请号：US10769330
申请日：2004-01-30
CPC分类号： G06F17/5054
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of the integrated circuit is configured to have a plurality of thread circuits and an interconnection topology amongst the plurality of thread circuits. Messages are concurrently processed using the plurality of thread circuits. Operation of at least one thread circuit of the plurality of thread circuits is controlled in accordance with control data received via the interconnection topology from at least one other thread circuit of the plurality of thread circuits.
摘要翻译： 描述了用于实现使用集成电路的消息处理系统的可编程架构。 在一个示例中，集成电路的可配置逻辑被配置为在多个线程电路之间具有多个线程电路和互连拓扑。 使用多个线程电路同时处理消息。 根据从多个线程电路的至少一个其它线程电路经由互连拓扑接收的控制数据来控制多个线程电路中的至少一个线程电路的操作。
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7.发明授权Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip 有权专用于可编程存储器架构和芯片上互连网络的方法和装置公开(公告)号：US07574680B1
公开(公告)日：2009-08-11
申请号：US11699097
申请日：2007-01-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.
摘要翻译： 描述了用于实现使用集成电路的消息处理系统的可编程架构。 在一个示例中，接收包括存储器系统的属性的规范数据。 响应于规范数据生成存储器系统的逻辑描述。 逻辑描述定义了存储器组件和存储器互连组件。 响应于逻辑描述生成存储器系统的物理描述。 物理描述包括与由存储器组件定义的集成电路相关联的存储器电路。 存储器电路包括由存储器互连部件定义的互连拓扑。
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8.发明授权Method and apparatus for a programmable interface of a soft platform on a programmable logic device 有权用于可编程逻辑器件上的软平台的可编程接口的方法和装置公开(公告)号：US07228520B1
公开(公告)日：2007-06-05
申请号：US10769331
申请日：2004-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, first attributes are defined for a plurality of threads within the integrated circuit. Second attributes are defined for a memory associated with the integrated circuit. Third attributes are defined for an interconnection topology associated with at least one of the memory and the plurality of threads. Fourth attributes are defined for an interface to at least one of the memory and the plurality of threads.
摘要翻译： 描述了用于实现使用集成电路的消息处理系统的可编程架构。 在一个示例中，为集成电路内的多个线程定义第一属性。 为与集成电路相关联的存储器定义第二属性。 为与存储器和多个线程中的至少一个相关联的互连拓扑定义第三属性。 为与至少一个存储器和多个线程的接口定义第四属性。
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公开(公告)号：US08015386B1
公开(公告)日：2011-09-06
申请号：US12059161
申请日：2008-03-31
IPC分类号： G06F12/00
CPC分类号： G06F12/0653
摘要： A configurable memory manager is configurable with various configuration parameters. The configurable memory manager has client ports for receiving requests for accessing memories and memory ports for accessing respective memories. The client and memory ports are each independently configurable to specify the parameter of a data width of the port. The configurable memory manager includes a switch and a translator. The translator translates a virtual address in each of the requests into an identifier of one of the memories and a physical address in the memory. The switch transfers each request from the client port receiving the request to the memory port for accessing the memory identified by the identifier for the virtual address in the request.
摘要翻译： 可配置的内存管理器可配置各种配置参数。 可配置存储器管理器具有用于接收访问存储器的请求的客户端口和用于访问相应存储器的存储器端口。 客户端和内存端口可以独立配置，以指定端口数据宽度的参数。 可配置存储器管理器包括开关和转换器。 翻译器将每个请求中的虚拟地址转换成存储器之一的标识符和存储器中的物理地址。 交换机将接收请求的客户端口的每个请求传送到存储器端口，以访问由请求中的虚拟地址的标识符标识的存储器。
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公开(公告)号：US07636909B1
公开(公告)日：2009-12-22
申请号：US11825372
申请日：2007-07-05
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/505
摘要： A method of automatically generating multithreaded datapaths from a circuit description can include identifying a plurality of process threads from a circuit description, wherein each process thread comprises at least one function, and representing each of the plurality of process threads as an order of operations graph including nodes that correspond to functions and edges that indicate dependencies between the functions. The method also can include identifying at least one conditional edge from the order of operations graphs. An updated circuit description can be generated that specifies a multiplexer for each conditional edge.
摘要翻译： 根据电路描述自动生成多线程数据路径的方法可以包括从电路描述中识别多个进程线程，其中每个进程线程包括至少一个功能，并将多个进程线程中的每一个表示为操作图的顺序包括 对应于指示功能之间的依赖关系的功能和边缘的节点。 该方法还可以包括从操作图的顺序识别至少一个条件边缘。 可以生成更新的电路描述，其为每个条件边缘指定多路复用器。
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