公开(公告)号：US08901649B2

公开(公告)日：2014-12-02

申请号：US13238858

申请日：2011-09-21

申请人： Chieh-Wei He ,  Shih-Yu Wang ,  Qi-An Xu

发明人： Chieh-Wei He ,  Shih-Yu Wang ,  Qi-An Xu

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/78 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66659

摘要： A semiconductor device, an electrostatic discharge protection device and manufacturing method thereof are provided. The electrostatic discharge protection device includes a gate, a gate dielectric layer, an N-type source region, an N-type drain region, an N-type doped region and a P-type doped region. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The N-type source region and the N-type drain region are disposed in the substrate at two sides of the gate, respectively. The N-type doped region is disposed in the N-type drain region and connects to the top of the N-type drain region. The P-type doped region is disposed under the N-type drain region and connects to the bottom of the N-type drain region.

摘要翻译： 提供半导体器件，静电放电保护器件及其制造方法。 静电放电保护器件包括栅极，栅极电介质层，N型源极区，N型漏极区，N型掺杂区和P型掺杂区。 栅介质层设置在基板上。 栅极设置在栅极电介质层上。 N型源极区域和N型漏极区域分别设置在栅极两侧的基板中。 N型掺杂区域设置在N型漏极区域中并且连接到N型漏极区域的顶部。 P型掺杂区域设置在N型漏极区域下方并连接到N型漏极区域的底部。

公开(公告)号：US20130069125A1

公开(公告)日：2013-03-21

申请号：US13238858

申请日：2011-09-21

申请人： CHIEH-WEI HE ,  Shih-Yu Wang ,  Qi-An Xu

发明人： CHIEH-WEI HE ,  Shih-Yu Wang ,  Qi-An Xu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66659

摘要： A semiconductor device, an electrostatic discharge protection device and manufacturing method thereof are provided. The electrostatic discharge protection device includes a gate, a gate dielectric layer, an N-type source region, an N-type drain region, an N-type doped region and a P-type doped region. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The N-type source region and the N-type drain region are disposed in the substrate at two sides of the gate, respectively. The N-type doped region is disposed in the N-type drain region and connects to the top of the N-type drain region. The P-type doped region is disposed under the N-type drain region and connects to the bottom of the N-type drain region.

摘要翻译： 提供半导体器件，静电放电保护器件及其制造方法。 静电放电保护器件包括栅极，栅极电介质层，N型源极区，N型漏极区，N型掺杂区和P型掺杂区。 栅介质层设置在基板上。 栅极设置在栅极电介质层上。 N型源极区域和N型漏极区域分别设置在栅极两侧的基板中。 N型掺杂区域设置在N型漏极区域中并且连接到N型漏极区域的顶部。 P型掺杂区域设置在N型漏极区域下方并连接到N型漏极区域的底部。

公开(公告)号：US08987779B2

公开(公告)日：2015-03-24

申请号：US13304383

申请日：2011-11-24

申请人： Qi-An Xu ,  Chieh-Wei He

发明人： Qi-An Xu ,  Chieh-Wei He

IPC分类号： H01L29/73 ,  H01L27/02 ,  H01L29/74

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： An ESD protection device including second P-type wells, first P+-type doped regions, first N+-type doped regions and a P-type substrate having a first P-type well, an N-type well and an N-type deep well is provided. The second P-type wells are disposed in the N-type deep well. The first P+-type doped regions and the first N+-type doped regions are respectively disposed in the first P-type well, the N-type well and the second P-type wells in alternation. The first P+-type doped region in the N-type well and the N-type deep well are electrically connected to the first connection terminal. The doped regions in the first P-type well and the P-type substrate are electrically connected to the second connection terminal. The second P-type wells and the first N+-type doped regions therein form a diode string connected in series between the first N+-type doped region of the N-type well and the second connection terminal.

摘要翻译： 一种ESD保护装置，包括第二P型阱，第一P +型掺杂区，第一N +型掺杂区和具有第一P型阱，N型阱和N型阱的P型衬底 被提供。 第二个P型井设置在N型深井中。 第一P +型掺杂区和第一N +型掺杂区分别设置在第一P型阱，N型阱和第二P型阱中。 N型阱和N型深阱中的第一P +型掺杂区域电连接到第一连接端子。 第一P型阱和P型衬底中的掺杂区域电连接到第二连接端子。 第二P型阱和其中的第一N +型掺杂区形成串联连接在N型阱的第一N +型掺杂区和第二连接端之间的二极管串。

公开(公告)号：US20130134479A1

公开(公告)日：2013-05-30

申请号：US13304383

申请日：2011-11-24

申请人： Qi-An Xu ,  Chieh-Wei He

发明人： Qi-An Xu ,  Chieh-Wei He

IPC分类号： H01L29/73

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： An ESD protection device including second P-type wells, first P+-type doped regions, first N+-type doped regions and a P-type substrate having a first P-type well, an N-type well and an N-type deep well is provided. The second P-type wells are disposed in the N-type deep well. The first P+-type doped regions and the first N+-type doped regions are respectively disposed in the first P-type well, the N-type well and the second P-type wells in alternation. The first P+-type doped region in the N-type well and the N-type deep well are electrically connected to the first connection terminal. The doped regions in the first P-type well and the P-type substrate are electrically connected to the second connection terminal. The second P-type wells and the first N+-type doped regions therein form a diode string connected in series between the first N+-type doped region of the N-type well and the second connection terminal.

摘要翻译： 一种ESD保护装置，包括第二P型阱，第一P +型掺杂区，第一N +型掺杂区和具有第一P型阱，N型阱和N型阱的P型衬底 被提供。 第二个P型井设置在N型深井中。 第一P +型掺杂区和第一N +型掺杂区分别设置在第一P型阱，N型阱和第二P型阱中。 N型阱和N型深阱中的第一P +型掺杂区域电连接到第一连接端子。 第一P型阱和P型衬底中的掺杂区域电连接到第二连接端子。 第二P型阱和其中的第一N +型掺杂区形成串联连接在N型阱的第一N +型掺杂区和第二连接端之间的二极管串。

公开(公告)号：US20130099297A1

公开(公告)日：2013-04-25

申请号：US13277796

申请日：2011-10-20

申请人： Chieh-Wei He ,  Qi-An Xu

发明人： Chieh-Wei He ,  Qi-An Xu

IPC分类号： H01L27/092

CPC分类号： H01L27/0285

摘要： An electrostatic discharge protection device electrically connected between a pad and an internal circuit is provided and includes a capacitor, a first resistor, a voltage-drop element and an NMOS transistor. A first end of the capacitor is electrically connected to the pad. A first end of the first resistor is electrically connected to a second end of the capacitor, and a second end of the first resistor is electrically connected to ground. The NMOS transistor and the voltage-drop element are connected in series between the pad and the ground, a gate of the NMOS transistor is electrically connected to the second end of the capacitor, and a bulk of the NMOS transistor is electrically connected to the ground.

摘要翻译： 提供电连接在焊盘和内部电路之间的静电放电保护装置，其包括电容器，第一电阻器，降压元件和NMOS晶体管。 电容器的第一端电连接到焊盘。 第一电阻器的第一端电连接到电容器的第二端，并且第一电阻器的第二端电连接到地。 NMOS晶体管和降压元件串联连接在焊盘和接地之间，NMOS晶体管的栅极电连接到电容器的第二端，并且大部分NMOS晶体管电连接到地 。