利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

68 条记录 (耗时 0.024 秒)

    METHOD FOR FABRICATING A METAL GATE STRUCTURE
    1.
    发明申请
    METHOD FOR FABRICATING A METAL GATE STRUCTURE 审中-公开
    制作金属结构结构的方法

    公开(公告)号：US20110012205A1

    公开(公告)日：2011-01-20

    申请号：US12889410

    申请日：2010-09-24

    申请人： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

    发明人： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

    IPC分类号： H01L29/49

    CPC分类号： H01L21/28123 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    摘要： A metal gate structure is disclosed. The metal gate structure includes: a semiconductor substrate having an active region and an isolation region; an isolation structure disposed in the isolation region; a first gate structure disposed on the active region; and a second gate structure disposed on the isolation structure, wherein the height of the second gate structure is different from the height of the first gate structure.

    摘要翻译： 公开了一种金属栅极结构。 金属栅极结构包括：具有有源区和隔离区的半导体衬底; 设置在所述隔离区域中的隔离结构; 设置在所述有源区上的第一栅极结构; 以及设置在所述隔离结构上的第二栅极结构，其中所述第二栅极结构的高度不同于所述第一栅极结构的高度。

    Method for manufacturing a CMOS device having dual metal gate
    4.
    发明授权
    Method for manufacturing a CMOS device having dual metal gate 有权
    制造具有双金属栅极的CMOS器件的方法

    公开(公告)号：US08685811B2

    公开(公告)日：2014-04-01

    申请号：US12013485

    申请日：2008-01-14

    申请人： Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Guang-Hwa Ma ,  Chin-Sheng Yang

    发明人： Chien-Ting Lin ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Guang-Hwa Ma ,  Chin-Sheng Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7843

    摘要： A method for manufacturing a CMOS device includes providing a substrate having a first active region and a second active region defined thereon, forming a first conductive type transistor and a second conductive type transistor respectively in the first and the second active regions, performing a salicide process, forming an ILD layer, performing a first etching process to remove a first gate of the first conductive type transistor and to form an opening while a high-K gate dielectric layer is exposed in a bottom of the opening, and forming at least a first metal layer in the opening.

    摘要翻译： 一种用于制造CMOS器件的方法，包括：提供具有第一有源区和限定在其上的第二有源区的衬底，分别在第一和第二有源区中形成第一导电型晶体管和第二导电型晶体管，执行自对准硅化物工艺 ，形成ILD层，执行第一蚀刻工艺以去除第一导电型晶体管的第一栅极并形成开口，同时高K栅极电介质层暴露在开口的底部，并形成至少第一 金属层在开口。

    METHOD FOR FABRICATING A METAL GATE STRUCTURE
    5.
    发明申请
    METHOD FOR FABRICATING A METAL GATE STRUCTURE 有权
    制作金属结构结构的方法

    公开(公告)号：US20110014773A1

    公开(公告)日：2011-01-20

    申请号：US12890725

    申请日：2010-09-27

    申请人： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

    发明人： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

    IPC分类号： H01L21/28 ,  H01L21/762

    CPC分类号： H01L21/28123 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    摘要： A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

    摘要翻译： 提供一种制造金属栅极结构的方法。 该方法包括：提供具有平坦化多晶硅材料的半导体衬底; 将平坦化的多晶硅材料图案化以形成至少第一栅极和第二栅极，其中第一栅极位于有源区上，而第二栅极至少部分地与隔离区重叠; 形成覆盖所述栅极的层间电介质材料; 平面化层间电介质材料，直到露出栅极并形成层间介电层; 执行蚀刻工艺以移除所述栅极以在所述层间电介质层内形成第一凹部和第二凹部; 在每个所述凹部的表面上形成栅极电介质材料; 在所述凹部内形成至少一种金属材料; 并执行平面化处理。

    Method for manufacturing a CMOS device having dual metal gate
    6.
    发明授权
    Method for manufacturing a CMOS device having dual metal gate 有权
    制造具有双金属栅极的CMOS器件的方法

    公开(公告)号：US07799630B2

    公开(公告)日：2010-09-21

    申请号：US12018214

    申请日：2008-01-23

    申请人： Chih-Hao Yu ,  Li-Wei Cheng ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Guang-Hwa Ma

    发明人： Chih-Hao Yu ,  Li-Wei Cheng ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ting Lin ,  Che-Hua Hsu ,  Guang-Hwa Ma

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

    摘要： A method for manufacturing a CMOS device having dual metal gate includes providing a substrate having at least two transistors of different conductive types and a dielectric layer covering the two transistors, planarizing the dielectric layer to expose gate conductive layers of the two transistors, forming a patterned blocking layer exposing one of the conductive type transistor, performing a first etching process to remove a portion of a gate of the conductive type transistor, reforming a metal gate, removing the patterned blocking layer, performing a second etching process to remove a portion of a gate of the other conductive type transistor, and reforming a metal gate.

    摘要翻译： 一种用于制造具有双金属栅极的CMOS器件的方法包括：提供具有不同导电类型的至少两个晶体管的衬底和覆盖两个晶体管的电介质层，平坦化介电层以暴露两个晶体管的栅极导电层，形成图案化 阻挡层暴露导电型晶体管之一，执行第一蚀刻工艺以去除导电型晶体管的栅极的一部分，重整金属栅极，去除图案化阻挡层，执行第二蚀刻工艺以去除部分 另一导电型晶体管的栅极，以及金属栅极的重整。

    METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE AND STRUCTURE OF STATIC RANDOM ACCESS MEMORY
    8.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE AND STRUCTURE OF STATIC RANDOM ACCESS MEMORY 有权
    制造半导体结构和静态随机存取存储器结构的方法

    公开(公告)号：US20090242997A1

    公开(公告)日：2009-10-01

    申请号：US12058208

    申请日：2008-03-28

    申请人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

    发明人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L27/11

    摘要： A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

    摘要翻译： 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填满第一开口。

    Method for fabricating semiconductor structure
    10.
    发明授权
    Method for fabricating semiconductor structure 有权
    半导体结构的制造方法

    公开(公告)号：US08193050B2

    公开(公告)日：2012-06-05

    申请号：US12907016

    申请日：2010-10-18

    申请人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

    发明人： Chih-Hao Yu ,  Li-Wei Cheng ,  Che-Hua Hsu ,  Tian-Fu Chiang ,  Cheng-Hsien Chou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Chien-Ting Lin ,  Guang-Hwa Ma

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11

    摘要： A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

    摘要翻译： 公开了一种制造半导体结构的方法。 提供具有第一晶体管的衬底，其具有第一虚拟栅极和具有第二虚拟栅极的第二晶体管。 第一晶体管和第二晶体管的导电类型不同。 同时去除第一和第二伪栅极以形成相应的第一和第二开口。 在基板上形成高k电介质层，第二导电层和第一低电阻导电层，并填充第一和第二开口，第一低电阻导电层填充第二开口。 第一开口中的第一低电阻导电层和第二导电层被去除。 然后在第一开口中形成第一导电层和第二低电阻导电层，第二低电阻导电层填充第一开口。