公开(公告)号：US20070216031A1

公开(公告)日：2007-09-20

申请号：US11308284

申请日：2006-03-15

申请人： Chih-Chao Yang ,  Nancy Klymko ,  Christopher Parks ,  Keith Wong

发明人： Chih-Chao Yang ,  Nancy Klymko ,  Christopher Parks ,  Keith Wong

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76862 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to treat a noble metal seed layer such that the treated noble metal seed layer is highly resistant to surface oxidation. The inventive oxidation-resistant noble metal seed layer has a low C content and/or a low nitrogen content.

摘要翻译： 提供了单镶嵌型或双镶嵌型的互连结构及其形成方法，其基本上减少了将导电材料电镀到贵金属种子层上的表面氧化问题。 根据本发明，使用氢等离子体处理来处理贵金属种子层，使得处理的贵金属种子层对表面氧化具有高度抗性。 本发明的抗氧化贵金属种子层具有低C含量和/或低氮含量。

公开(公告)号：US20070275557A1

公开(公告)日：2007-11-29

申请号：US11839260

申请日：2007-08-15

申请人： Chih-Chao Yang ,  Nancy Klymko ,  Christopher Parks ,  Keith Wong

发明人： Chih-Chao Yang ,  Nancy Klymko ,  Christopher Parks ,  Keith Wong

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76862 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to treat a noble metal seed layer such that the treated noble metal seed layer is highly resistant to surface oxidation. The inventive oxidation-resistant noble metal seed layer has a low C content and/or a low nitrogen content.

公开(公告)号：US20080045039A1

公开(公告)日：2008-02-21

申请号：US11873721

申请日：2007-10-17

申请人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

发明人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

IPC分类号： H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

公开(公告)号：US20080036007A1

公开(公告)日：2008-02-14

申请号：US11875217

申请日：2007-10-19

申请人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

发明人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

公开(公告)号：US20070007548A1

公开(公告)日：2007-01-11

申请号：US11160705

申请日：2005-07-06

申请人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

发明人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

IPC分类号： H01L21/8234 ,  H01L27/10 ,  H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。