摘要:
A signal detecting method and a receiver using the same are provided. The method includes the following steps. A receiving signal vector y is received through a number of channels, wherein the receiving signal vector y corresponds to a transmitting signal vector x transmitted by at least one of the channels. A channel matrix H is determined, wherein the channel matrix H represents at least one of the channels. A factorization matrix D is chosen, wherein D is invertible to make the channel matrix H expressed as H={tilde over (H)}D, and {tilde over (H)} is a corresponding channel matrix. The factorization matrix D is determined to make an expected value of the signal estimate error become smaller. The receiving signal vector y is detected to estimate the transmitting signal vector x according to the corresponding channel matrix {tilde over (H)} and the factorization matrix D.
摘要:
A signal detecting method and a receiver using the same are provided. The method includes the following steps. A receiving signal vector y is received through a number of channels, wherein the receiving signal vector y corresponds to a transmitting signal vector x transmitted by at least one of the channels. A channel matrix H is determined, wherein the channel matrix H represents at least one of the channels. A factorization matrix D is chosen, wherein D is invertible to make the channel matrix H expressed as H={tilde over (H)}D, and {tilde over (H)} is a corresponding channel matrix. The factorization matrix D is determined to make an expected value of the signal estimate error become smaller. The receiving signal vector y is detected to estimate the transmitting signal vector x according to the corresponding channel matrix {tilde over (H)} and the factorization matrix D.
摘要:
Multiple applications upon an IC microprocessor are protected with bi-modal CPU operation, either application or system mode, using an operation flag determining the mode and dependent upon a mode change interrupt which clears all working memory unnecessary to operation in the next mode. Access authorization setting program and data memory boundaries according to the particular custom command in comparison registers is utilized in application initialization. From application mode, data files are accessed only through a system subroutine. Request of an address beyond the territory assigned to the custom command utilized results in a hardware interrupt which clears all working memory and registers unnecessary to forward a status word indicating abnormal termination. Application completion forwards the result with a status word indicating successful completion. Operation results either in successful completion or abnormal termination without possible access of any other application contained upon the IC card (10).
摘要:
A timing recovery apparatus for compensating a sampling frequency offset of an input signal is provided. The timing recovery apparatus includes a timing error corrector configured to generate an output signal according to the input signal and a calibration signal, a gain controller configured to adjust at least one of a signal edge low-frequency error component and a signal edge high-frequency error component of the output signal and accordingly generate an adjusted signal, a timing error detector configured to generate an error signal according to the adjusted signal, and a calibration signal generator coupled to the timing error detector and the timing error corrector, for generating the calibration signal according to the error signal and outputting the calibration signal to the timing error corrector to compensate the sampling frequency offset of the input signal.
摘要:
Alarm control circuitry is provided for a Universal Serial Bus (USB) port connectible device including an alarm generator emitting an audible alarm when powered by internal voltage from a capacitor charged by external voltage from a computer during connection of the device to a computer and actuated with a power off detection circuit in the condition that termination of power from the computer to the device is detected. Provision for an optional base unit with passive RFID in the alarm control circuitry includes an RF transceiver, ID reader, timer and counter causing alarm activation if a ‘reflected’ RF signal is not received in a certain amount of time. An exemplary power off detection circuit outputs an alarm control signal digital logic ‘1’ in alarm generator actuation using an AND gate fed by internal voltage and external voltage reverse logic.
摘要:
Reminding of the owner of a Universal Serial Bus (USB) port connectible device that the same has been left connected to a USB port of a powered computer is provided by an alarm disposed on a portable base for the device activated by cessation of reception of a limited range radio frequency (RF) signal. Transmission is powered by the computer through the USB port. The portable base has an independent power source for reception/alarm circuitry preferably switched on by separation of a USB port connectible device and/or signalling attachment from the portable base and switched off by physical reunion of the same. Alarm activation while retrieving the USB port connectible device from the USB port of a computer is avoided with an alarm activation delay exceeding in duration a transmission interval minimizing the likelihood of RF signal interference between multiple proximate reminders or other signals of the same RF. An identification (ID) number carried by the RF signal and recognized by a portable base thereby associated with a particular USB port connectible device and/or signalling attachment avoids defeat of alarm activation by reception of another signal of the same RF.
摘要:
Multiple applications upon an IC microprocessor are protected with bi-modal CPU operation, either in application mode or system mode, using an operation flag determining the mode and a functional interrupt with each mode change. Direct subroutine calling is replaced by a software interrupt which clears all working memory and registers except those holding parameters including the return address placed in stack. Access authorization utilizing a comparison register containing application and system memory boundaries according to the particular custom command utilized is associated with a mode change interrupt in application initialization. System subroutine running involves two mode change interrupts, from application to system and back, and includes access authorization. Request of an address beyond the territory assigned to the custom command utilized results in a hardware interrupt which clears all working memory and registers in the system mode and except that necessary to forward a status word indicating abnormal termination. Application completion forwards the result with a status word indicating successful completion. Hard-wired bi-modal CPU operation utilizing a mode change interrupt which saves parameters in stack but clears all other registers and working memory and utilizes a comparison register to authorize the system address prior to return to application mode with the return address held in stack ensures that operation in the application authorized by the custom command utilized will result either in successful completion or abnormal termination without possible access of any other application contained upon the IC card.