公开(公告)号：US06800510B2

公开(公告)日：2004-10-05

申请号：US10289470

申请日：2002-11-06

申请人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

发明人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

IPC分类号： H01L2100

CPC分类号： H01L27/1248 ,  G02F1/136213 ,  H01L27/1255 ,  H01L29/42384

摘要： A method of controlling the capacitance of the TFT-LCD storage capacitor is provided. The gate dielectric layer of the TFT is composed of a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when a doped and an undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled; thereby the capacitance of the storage capacitor can be controlled.

摘要翻译： 提供了一种控制TFT-LCD存储电容器的电容的方法。 TFT的栅介质层由氮化硅层，电介质层和氮化硅层组成，非晶硅层在电介质层上的蚀刻选择性不小于约5.0。 因此，当蚀刻掺杂的和未掺杂的非晶硅层以形成源极/漏极堆叠层时或者蚀刻导电层以在栅极介电层上形成栅极时，介电层可以是蚀刻停止层。 因此，可以控制介电层厚度; 从而可以控制存储电容器的电容。

公开(公告)号：US07087469B2

公开(公告)日：2006-08-08

申请号：US10934242

申请日：2004-09-03

申请人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

发明人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

IPC分类号： H01L21/00

CPC分类号： H01L27/1248 ,  G02F1/136213 ,  H01L27/1255 ,  H01L29/42384

摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.

摘要翻译： 公开了一种控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法。 在某些实施例中，该方法包括：i）在透明基底上形成硅岛和底部电极，硅岛具有位于中心部分上的未掺杂区域，以及分别位于两侧的两个掺杂区域，ii）形成第一 氮化硅层，以及iii）在所述硅岛的未掺杂区域上形成包括第二氮化硅层和导电层的堆叠层，并且所述层叠层的第一导电层用作薄的栅极 薄膜晶体管，其中导电层在电介质层上的蚀刻选择率不小于约5.0。

公开(公告)号：US06953715B2

公开(公告)日：2005-10-11

申请号：US10934014

申请日：2004-09-03

申请人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

发明人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

IPC分类号： G02F1/1362 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/13 ,  H01L29/423 ,  H01L21/00

CPC分类号： H01L27/1248 ,  G02F1/136213 ,  H01L27/1255 ,  H01L29/42384

摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.

公开(公告)号：US07145172B2

公开(公告)日：2006-12-05

申请号：US10932828

申请日：2004-09-02

申请人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

发明人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

IPC分类号： H01L31/0376 ,  H01L21/00

CPC分类号： H01L27/1248 ,  G02F1/136213 ,  H01L27/1255 ,  H01L29/42384

摘要： A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.

摘要翻译： 提供薄膜晶体管液晶显示器（TFT-LCD）的薄膜晶体管阵列基板。 TFT的栅介质层包括氮化硅层，电介质层和氮化硅层，并且非晶硅层在电介质层上的蚀刻选择性不小于约5.0。 因此，当掺杂和非掺杂非晶硅层被蚀刻以形成源极/漏极堆叠层时，介电层可以是蚀刻停止层，或蚀刻导电层以在栅极介电层上形成栅极。 因此，可以控制介电层厚度，从而可以控制存储电容器的电容。

公开(公告)号：US20050037533A1

公开(公告)日：2005-02-17

申请号：US10934014

申请日：2004-09-03

申请人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

发明人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

IPC分类号： G02F1/1362 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/13 ,  H01L29/423 ,  H01L21/00

CPC分类号： H01L27/1248 ,  G02F1/136213 ,  H01L27/1255 ,  H01L29/42384

摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming an undoped amorphous silicon layer on a silicon nitride layer, ii) forming an etching mask on the undoped amorphous silicon layer, and iii) forming two doped amorphous silicon layers on portion of the undoped amorphous silicon layer and the etching mask, the two doped amorphous silicon layers being spaced apart and located on either side of the gate, wherein an etching selectivity ratio of the undpoed and doped amorphous silicon layers over the dielectric layer being not less than about 5.0.

摘要翻译： 公开了一种控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法。 在某些实施例中，该方法包括：i）在氮化硅层上形成未掺杂的非晶硅层，ii）在未掺杂的非晶硅层上形成蚀刻掩模，以及iii）在未掺杂的非晶硅的部分上形成两个掺杂非晶硅层 层和蚀刻掩模，两个掺杂的非晶硅层间隔开并位于栅极的任一侧，其中在电介质层上的未掺杂和掺杂的非晶硅层的蚀刻选择率不小于约5.0。

公开(公告)号：US20050032263A1

公开(公告)日：2005-02-10

申请号：US10934242

申请日：2004-09-03

申请人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

发明人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

IPC分类号： G02F1/1362 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/13 ,  H01L29/423 ,  H01L21/00

CPC分类号： H01L27/1248 ,  G02F1/136213 ,  H01L27/1255 ,  H01L29/42384

摘要： A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.

摘要翻译： 公开了一种控制薄膜晶体管液晶显示器（TFT-LCD）存储电容器的电容的方法。 在某些实施例中，该方法包括：i）在透明基底上形成硅岛和底部电极，硅岛具有位于中心部分上的未掺杂区域，以及分别位于两侧的两个掺杂区域，ii）形成第一 氮化硅层，以及iii）在所述硅岛的未掺杂区域上形成包括第二氮化硅层和导电层的堆叠层，并且所述层叠层的第一导电层用作薄的栅极 薄膜晶体管，其中导电层在电介质层上的蚀刻选择率不小于约5.0。

公开(公告)号：US20050023533A1

公开(公告)日：2005-02-03

申请号：US10932828

申请日：2004-09-02

申请人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

发明人： Chih-Yu Peng ,  Wei-Chuan Lin ,  Chian-Chih Hsiao ,  Ta-Ko Chuang ,  Chun-Hung Chu ,  Chih-Lung Lin ,  Chin-Mao Lin

IPC分类号： G02F1/1362 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/13 ,  H01L29/423 ,  H01L29/04

CPC分类号： H01L27/1248 ,  G02F1/136213 ,  H01L27/1255 ,  H01L29/42384

摘要： A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.

摘要翻译： 提供薄膜晶体管液晶显示器（TFT-LCD）的薄膜晶体管阵列基板。 TFT的栅介质层包括氮化硅层，电介质层和氮化硅层，并且非晶硅层在电介质层上的蚀刻选择性不小于约5.0。 因此，当掺杂和非掺杂非晶硅层被蚀刻以形成源极/漏极堆叠层时，介电层可以是蚀刻停止层，或蚀刻导电层以在栅极介电层上形成栅极。 因此，可以控制介电层厚度，从而可以控制存储电容器的电容。

公开(公告)号：US08159627B2

公开(公告)日：2012-04-17

申请号：US12405805

申请日：2009-03-17

申请人： Wei-Chuan Lin ,  Lung-chuan Chang

发明人： Wei-Chuan Lin ,  Lung-chuan Chang

IPC分类号： G02F1/1333

CPC分类号： G02F1/136259 ,  G02F2001/136254 ,  G02F2202/103 ,  H01L27/124

摘要： Disclosed is a pixel layout structure capable of increasing the capability of detecting amorphous silicon (a-Si) residue defects and a method for manufacturing the same. Wherein, an a-Si dummy layer is disposed on either one side or both sides of each data line. The design of such an a-Si dummy layer is utilized, so that in an existing testing conditions (by making use of an existing automatic array tester in carrying out the test), in case that there exists an a-Si residue in a pixel, the pixel having defects can be detected through an enhanced capacitance coupling effect and an electron conduction effect. Therefore, through the application of the above-mentioned design, the capability of an automatic array tester can effectively be increased in detecting a defective pixel having a-Si residues.

摘要翻译： 公开了能够提高检测非晶硅（a-Si）残留缺陷的能力的像素布局结构及其制造方法。 其中，a-Si虚拟层设置在每条数据线的一侧或两侧。 使用这种a-Si虚拟层的设计，使得在现有的测试条件（通过利用现有的自动阵列测试仪进行测试）中，在像素中存在a-Si残留的情况下 可以通过增强的电容耦合效应和电子传导效应来检测具有缺陷的像素。 因此，通过应用上述设计，可以有效地提高自动阵列测试仪的检测能力，以检测具有a-Si残留的缺陷像素。

公开(公告)号：US20050082492A1

公开(公告)日：2005-04-21

申请号：US10965404

申请日：2004-10-14

申请人： Wei-Chuan Lin ,  Kei-Hsiung Yang

发明人： Wei-Chuan Lin ,  Kei-Hsiung Yang

IPC分类号： G01T1/24 ,  H01L27/14 ,  H01L27/146 ,  H01L29/786 ,  H01L31/02

CPC分类号： H01L27/14609 ,  H01L27/14658 ,  H01L29/78645

摘要： An X-ray image detector with a tandem-gate TFT. A storage capacitor comprises a bottom conductive layer connected to a ground line, and a top conductive layer insulated from the bottom conductive layer by an insulating layer. A thin film transistor controls release of the electric charge stored in the storage capacitor, wherein the thin film transistor comprises two electrically connected in series channel regions.

摘要翻译： 具有串联栅极TFT的X射线图像检测器。 存储电容器包括连接到接地线的底部导电层和通过绝缘层与底部导电层绝缘的顶部导电层。 薄膜晶体管控制存储在存储电容器中的电荷的释放，其中薄膜晶体管包括两个电连接的串联沟道区。