公开(公告)号：US06970477B2

公开(公告)日：2005-11-29

申请号：US09683647

申请日：2002-01-29

Applicant: Ching-Fu Chuang ,  Chia-Hsin Chen

Inventor： Ching-Fu Chuang ,  Chia-Hsin Chen

IPC: H04L1/08 ,  H04L12/54

CPC classification number: H04L1/08

Abstract: A data transmission circuit has an internal circuit for providing data, a register electrically connected to the internal circuit for temporarily storing the data transmitted from the input internal circuit, and a control circuit for controlling operations of the data transmission circuit. If data inputted to the register is specific data, the internal circuit will repeatedly output the specific data to the register so as to prolong transmission time of the specific data.

Abstract translation: 数据传输电路具有用于提供数据的内部电路，电连接到内部电路的用于临时存储从输入内部电路发送的数据的寄存器和用于控制数据传输电路的操作的控制电路。 如果输入到寄存器的数据是特定数据，则内部电路将重复地将特定数据输出到寄存器，以便延长特定数据的传输时间。

公开(公告)号：US20090172264A1

公开(公告)日：2009-07-02

申请号：US12238152

申请日：2008-09-25

Applicant: Chien-Ping Chung ,  Chia-Hsin Chen ,  Ming-Che Liu

Inventor： Chien-Ping Chung ,  Chia-Hsin Chen ,  Ming-Che Liu

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F12/0246

Abstract: A data accessing command integration method includes the following steps. Firstly, M data accessing commands are sequentially received through a bus, wherein N data accessing commands contained in the M data accessing commands have the same command type and comply with a sequential address relationship. Next, the N data accessing commands are re-ordered according to the addressing sequence, so that a first data corresponding to the re-ordered N data accessing commands are sequentially accessed in the data memory.

Abstract translation: 数据访问命令集成方法包括以下步骤。 首先，通过总线顺序地接收M个数据访问命令，其中包含在M个数据访问命令中的N个数据访问命令具有相同的命令类型并且遵循顺序地址关系。 接下来，根据寻址序列重新排序N个数据访问命令，从而在数据存储器中顺序地访问对应于重新排序的N个数据访问命令的第一数据。

公开(公告)号：US06446172B1

公开(公告)日：2002-09-03

申请号：US09335602

申请日：1999-06-18

Applicant: Chia-Hsin Chen ,  Nai-Shung Chang

Inventor： Chia-Hsin Chen ,  Nai-Shung Chang

IPC: G06F1208

CPC classification number: G06F12/0859 ,  G06F13/161

Abstract: A memory access control method and system is provided for use on a computer system to control the memory access operation by a central processing unit (CPU) to a memory unit in a more efficient manner than the prior art. This memory access control method and system is characterized by, for each read request from the CPU, the prompt transfer of the corresponding internal read-request signal to the memory control unit, right after it is issued and without waiting until the CPU issues the L1 write-back signal of the current read request. If the current read request is a hit to the cache memory, a read-stop signal is promptly issued to stop the current read operation on the memory unit, and then a cache write-back operation is performed to write the cache data back into the memory unit. This method and system can help reduce the period of waiting states by the CPU, thus increasing the overall memory access performance by the CPU and the overall system performance of the computer system.

Abstract translation: 提供存储器访问控制方法和系统，用于在计算机系统上以比现有技术更有效的方式将中央处理单元（CPU）的存储器访问操作控制到存储器单元。 这种存储器访问控制方法和系统的特征在于，对于来自CPU的每个读取请求，在相应的内部读取请求信号被发出之后立即将其传送到存储器控制单元，并且不等待直到CPU发出L1 当前读取请求的回写信号。 如果当前读取请求是对高速缓存存储器的命中，则立即发出读停止信号以停止对存储器单元的当前读取操作，然后执行高速缓存回写操作以将高速缓存数据写回到 存储单元 该方法和系统可以帮助减少CPU等待状态的时间，从而提高CPU的整体内存访问性能以及计算机系统的整体系统性能。

公开(公告)号：US06278641B1

公开(公告)日：2001-08-21

申请号：US09578234

申请日：2000-05-24

Applicant: Chia-Hsin Chen ,  Jiin Lai

Inventor： Chia-Hsin Chen ,  Jiin Lai

IPC: G11C700

CPC classification number: G11C7/222 ,  G11C7/22 ,  G11C11/4076

Abstract: An apparatus and method capable of programmably delaying a clock of a memory. The apparatus and method utilize the BIOS, external electric switches or other logic devices to selectively delay the clock of the DRAM and/or the internal clock of the north bridge, by which the DRAM has enough setup time at the rising edge of work clock to correctly read out the command word. The north bridge can then correctly receive data from the DRAM module and transfer the data to the CPU or AGP. Therefore, the memory can function normally even if the memory is operated at high speed or with heavy loading.

Abstract translation: 一种能够可编程地延迟存储器的时钟的装置和方法。 该装置和方法利用BIOS，外部电气开关或其他逻辑装置来选择性地延迟DRAM的时钟和/或北桥的内部时钟，由此DRAM在工作时钟的上升沿具有足够的建立时间 正确读出命令字。 然后，北桥可以从DRAM模块正确接收数据，并将数据传输到CPU或AGP。 因此，即使存储器以高速或大负载运行，存储器也能正常工作。

公开(公告)号：US09104546B2

公开(公告)日：2015-08-11

申请号：US13014735

申请日：2011-01-27

Applicant: Chi-Lung Wang ,  Chia-Hsin Chen ,  Chien-Cheng Lin

Inventor： Chi-Lung Wang ,  Chia-Hsin Chen ,  Chien-Cheng Lin

IPC: G06F13/12 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/10 ,  G06F2212/7201

Abstract: A method for performing block management is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: adjusting a dynamic threshold according to at least one condition; and comparing a valid/invalid page count of a specific block of the plurality of blocks with the dynamic threshold to determine whether to erase the specific block. An associated memory device and a controller thereof are also provided, where the memory device includes the Flash memory and the controller. In particular, the controller includes a read only memory (ROM) arranged to store a program code, and further includes a microprocessor arranged to execute the program code to control access to the Flash memory and manage the plurality of blocks, where under control of the microprocessor, the controller operates according to the method.

Abstract translation: 提供了一种执行块管理的方法。 该方法应用于闪速存储器的控制器，其中闪速存储器包括多个块。 该方法包括：根据至少一个条件调整动态阈值; 以及将所述多个块中的特定块的有效/无效页面计数与所述动态阈值进行比较，以确定是否擦除所述特定块。 还提供了一种相关联的存储器件及其控制器，其中存储器件包括闪存和控制器。 特别地，控制器包括被布置为存储程序代码的只读存储器（ROM），并且还包括微处理器，其被布置为执行程序代码以控制对闪存的访问并管理多个块，其中在 微处理器，控制器根据方法进行操作。

公开(公告)号：US08195870B2

公开(公告)日：2012-06-05

申请号：US12050205

申请日：2008-03-18

Applicant: Chia-Hsin Chen

Inventor： Chia-Hsin Chen

IPC: G06F12/00

CPC classification number: G06F12/0246

Abstract: The invention provides a method for handling data updating of a flash memory. In one embodiment, the flash memory comprises a mother block comprising a plurality of updated pages to be updated. First, a spare block, recording no data, is popped as a file allocation table (FAT) block corresponding to the mother block. Data for updating the updated pages of the mother block is then written to a plurality of replacing pages of the FAT block. Finally, a plurality of mapping relationships between the replacing pages and the updated pages are recorded in a page mapping table stored in the FAT block.

Abstract translation: 本发明提供了一种处理闪速存储器的数据更新的方法。 在一个实施例中，闪速存储器包括母块，其包括要更新的多个更新的页面。 首先，将不记录数据的备用块作为与母块对应的文件分配表（FAT）块而弹出。 然后将用于更新母块的更新页面的数据写入FAT块的多个替换页面。 最后，替换页面和更新页面之间的多个映射关系被记录在存储在FAT块中的页面映射表中。

公开(公告)号：US20090248965A1

公开(公告)日：2009-10-01

申请号：US12401466

申请日：2009-03-10

Applicant: Yuan-Huei Lee ,  Chi Chang ,  Chia-Hsin Chen ,  Ming-Che Liu

Inventor： Yuan-Huei Lee ,  Chi Chang ,  Chia-Hsin Chen ,  Ming-Che Liu

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7208

Abstract: A hybrid flash memory device and a control method of the hybrid flash memory device are provided. The hybrid flash memory device includes a micro controller connected to a host bus for receiving data to be written in the hybrid flash memory device from a host via the host bus; and a memory module coupled to the micro controller. The flash module includes a first type of flash memory and a second type of flash memory. The data are determined to be written in a first log block of the first type of flash memory when the data size is not greater than a predetermined data size. On the contrary, the data are determined to be written in a second log block of the second type of flash memory when the data size is greater than the predetermined data size.

Abstract translation: 提供一种混合式闪速存储装置和混合式闪速存储装置的控制方法。 混合式闪速存储装置包括连接到主机总线的微控制器，用于经由主机总线从主机接收要写入混合式闪速存储器装置的数据; 以及耦合到所述微控制器的存储器模块。 闪存模块包括第一类型的闪存和第二类闪存。 当数据大小不大于预定数据大小时，数据被确定为被写入第一类闪速存储器的第一对数块中。 相反，当数据大小大于预定数据大小时，确定数据被写入第二类闪存的第二对数块中。

公开(公告)号：US20080288818A1

公开(公告)日：2008-11-20

申请号：US12030209

申请日：2008-02-13

Applicant: Wen-Yueh Lai ,  Chia-Hsin Chen

Inventor： Wen-Yueh Lai ,  Chia-Hsin Chen

IPC: G06F11/07

CPC classification number: G06F1/305 ,  G06F3/14 ,  G09G2330/02 ,  G09G2330/08

Abstract: In an application system of a liquid crystal display, for protecting transmissions between a master terminal and a slave terminal, effects caused by an unstable power source of the slave terminal have to be reduced to a lowest degree. When the application system is reset or under normal operations with the power source having a suddenly-decreased or suddenly-unstable voltage level, the transmission between the master terminal and the slave terminal have to be terminated, and related data of the terminated transmission is temporarily stored. When the voltage of the slave terminal is confirmed to reach to a stable voltage over a predetermined duration, the transmission may be restored by the stored data.

Abstract translation: 在液晶显示器的应用系统中，为了保护主终端和从属终端之间的传输，必须将从属终端的不稳定电源引起的影响降低到最低程度。 当应用系统复位或正常工作时，电源突然降低或突然不稳定的电压电平，主终端和从终端之间的传输必须终止，终止传输的相关数据暂时 存储。 当确定从站终端的电压在预定时间内达到稳定的电压时，可以通过存储的数据恢复传输。

公开(公告)号：US07400623B2

公开(公告)日：2008-07-15

申请号：US11142283

申请日：2005-06-02

Applicant: Chia-Hsin Chen

Inventor： Chia-Hsin Chen

IPC: H04L12/56 ,  H04L12/43

CPC classification number: H04L29/12009 ,  H04L29/12839 ,  H04L45/7453 ,  H04L49/90 ,  H04L49/901 ,  H04L61/6022

Abstract: A method for managing medium access control (MAC) address and related apparatus are provided, including an MAC address learning method and an MAC addresses inquiring method. The learning method includes the steps of: mapping an MAC address to a designated slot and a companion slot in an address table; if said designated slot being empty, learning said MAC address into said designated slot; and if said designated slot being non-empty, said companion slot being empty and the content of said designated slot being non-static, moving the content of said designated slot to said companion slot and modifying a bit of the higher part of said MAC address in said companion slot and learning said MAC address into said designated slot.

Abstract translation: 提供了一种用于管理介质访问控制（MAC）地址和相关装置的方法，包括MAC地址学习方法和MAC地址查询方法。 该学习方法包括以下步骤：将MAC地址映射到地址表中的指定时隙和伴随时隙; 如果所述指定的时隙是空的，则将所述MAC地址学习到所述指定的时隙中; 并且如果所述指定时隙不为空，则所述伴随时隙为空，并且所述指定时隙的内容是非静态的，将所述指定时隙的内容移动到所述伴随时隙，并修改所述MAC地址的较高部分的一位 在所述伴侣时隙中，将所述MAC地址学习到所述指定时隙。

公开(公告)号：US20070146170A1

公开(公告)日：2007-06-28

申请号：US11424612

申请日：2006-06-16

Applicant: Chia-Hsin Chen ,  Chiu-Yuan Lin ,  Bor-Yuh Chang

Inventor： Chia-Hsin Chen ,  Chiu-Yuan Lin ,  Bor-Yuh Chang

IPC: H03M7/00

CPC classification number: H04N5/14

Abstract: A video processing method and apparatus to employing an analog user interface and a digital video decoder. A working mode is provided, according to which analog control signals from the analog user interface are selectively directed to an analog-to-digital converter. The analog control signal is converted to digital control signal to accordingly control the digital video decoder.

Abstract translation: 一种采用模拟用户界面和数字视频解码器的视频处理方法和装置。 提供工作模式，根据该工作模式，来自模拟用户界面的模拟控制信号被选择性地引导到模数转换器。 模拟控制信号被转换为数字控制信号，从而相应地控制数字视频解码器。