公开(公告)号：US20060018633A1

公开(公告)日：2006-01-26

申请号：US10710594

申请日：2004-07-22

Applicant: Ching-Yu Tsai ,  Chi-Hui Huang

Inventor： Ching-Yu Tsai ,  Chi-Hui Huang

IPC: H04N5/781

CPC classification number: H04N5/765 ,  G11B20/10527 ,  G11B2020/10537 ,  G11B2020/10638 ,  G11B2020/10759

Abstract: A digital video (DV) storage system comprises an interface module receiving an incoming signal and converting the incoming signal into an incoming bit-stream; a DV demuxer directly connected to the interface module for receiving the incoming bit-stream, wherein the DV demuxer de-multiplexes received blocks in the incoming bit-stream into at least video blocks being in video sections and audio blocks being in audio sections; and memory coupled to the DV demuxer for storing the video blocks and audio blocks. By directly connecting the interface module to the DV demuxer, and by not buffering the incoming bit-stream outside the interface module and the DV demuxer, the memory bandwidth requirement of the memory is greatly reduced, and the interface module and the DV demuxer can be easily implemented together in a single IC.

Abstract translation: 数字视频（DV）存储系统包括接收模块，接收输入信号并将输入信号转换成输入位流; 直接连接到所述接口模块的DV解复用器，用于接收所述输入比特流，其中所述DV解复用器将所述输入比特流中的接收块解复用为至少在音频部分中的视频部分和音频块中的视频块; 以及耦合到DV解复用器的存储器以用于存储视频块和音频块的存储器。 通过将接口模块直接连接到DV解复用器，并且通过不缓冲接口模块和DV解复用器之外的输入位流，大大减少了存储器的存储器带宽需求，并且接口模块和DV解复用器可以 可以在单个IC中轻松实现。

公开(公告)号：US07362905B2

公开(公告)日：2008-04-22

申请号：US10930875

申请日：2004-08-31

Applicant: Hong-Hui Chen ,  Chung-Yen Lu ,  Chi-Hui Huang

Inventor： Hong-Hui Chen ,  Chung-Yen Lu ,  Chi-Hui Huang

IPC: G06K9/36

CPC classification number: H04N19/132 ,  H04N9/8047 ,  H04N9/8063 ,  H04N19/156 ,  H04N19/18 ,  H04N19/184 ,  H04N19/423 ,  H04N19/61

Abstract: Methods and systems for multi-stage DV encoding and decoding. A skip command may be issued by a microprocessor or DRAM controller via a physical link when DRAM bandwidth is overtaxed. Corresponding encoding and decoding systems implementing the proposed DV encoding or decoding method are also provided.

Abstract translation: 用于多级DV编码和解码的方法和系统。 当DRAM带宽过高时，可通过物理链路由微处理器或DRAM控制器发出跳过命令。 还提供了实现所提出的DV编码或解码方法的相应编码和解码系统。

公开(公告)号：US20060045359A1

公开(公告)日：2006-03-02

申请号：US10930875

申请日：2004-08-31

Applicant: Hong-Hui Chen ,  Chung-Yen Lu ,  Chi-Hui Huang

Inventor： Hong-Hui Chen ,  Chung-Yen Lu ,  Chi-Hui Huang

IPC: G06K9/36

CPC classification number: H04N19/132 ,  H04N9/8047 ,  H04N9/8063 ,  H04N19/156 ,  H04N19/18 ,  H04N19/184 ,  H04N19/423 ,  H04N19/61

Abstract: Methods and systems for multi-stage DV encoding and decoding. A skip command may be issued by a microprocessor or DRAM controller via a physical link when DRAM bandwidth is overtaxed. Corresponding encoding and decoding systems implementing the proposed DV encoding or decoding method are also provided.

Abstract translation: 用于多级DV编码和解码的方法和系统。 当DRAM带宽过高时，可通过物理链路由微处理器或DRAM控制器发出跳过命令。 还提供了实现所提出的DV编码或解码方法的相应编码和解码系统。

公开(公告)号：US20050141556A1

公开(公告)日：2005-06-30

申请号：US11017282

申请日：2004-12-20

Applicant: Chung-Yen Lu ,  Hong-Hui Chen ,  Chi-Hui Huang

Inventor： Chung-Yen Lu ,  Hong-Hui Chen ,  Chi-Hui Huang

IPC: H04J3/16 ,  H04N7/26 ,  H04N7/30

CPC classification number: H04N21/2343 ,  H04N19/60

Abstract: The present invention is a bits stream control system for digital data. The bits stream control system comprises an encoder, a bits stream truncator, and a buffer. The encoder is used for encoding the digital data into a plurality of bits streams. The bits stream truncator is used for truncating or not truncating each of the bits streams to generate a plurality of corresponding modified bits streams according to a predetermined bit budget policy. The buffer is used for storing the modified bits streams.

Abstract translation: 本发明是用于数字数据的比特流控制系统。 比特流控制系统包括编码器，比特流截断器和缓冲器。 编码器用于将数字数据编码成多个比特流。 比特流截断器用于截断或不截断每个比特流以根据预定的比特预算策略生成多个对应的修改比特流。 缓冲区用于存储修改的比特流。