公开(公告)号：US20060068529A1

公开(公告)日：2006-03-30

申请号：US11281182

申请日：2005-11-16

申请人： Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

发明人： Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC分类号： H01L21/8232

CPC分类号： G11C16/0483 ,  G11C2216/04 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

公开(公告)号：US20050145923A1

公开(公告)日：2005-07-07

申请号：US10753103

申请日：2004-01-06

申请人： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

发明人： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

IPC分类号： G11C16/04 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： NAND flash memory cell array and fabrication process in which control gates and floating gates are stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other and

摘要翻译： NAND闪速存储器单元阵列和制造工艺，其中控制栅极和浮置栅极成对地堆叠成排列在位线扩散和公共源极扩散之间的行，每对堆叠栅极的两侧具有选择栅极。 每个堆叠对中的门彼此自对齐，并且时，文本丢失或难以辨认

公开(公告)号：US07217621B2

公开(公告)日：2007-05-15

申请号：US11281182

申请日：2005-11-16

申请人： Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

发明人： Chiou-Feng Chen ,  Caleb Yu-Sheng Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC分类号： H01L21/336

CPC分类号： G11C16/0483 ,  G11C2216/04 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

摘要翻译： 自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。 每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位 排列源扩散。 擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合 其他大门。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

公开(公告)号：US07037787B2

公开(公告)日：2006-05-02

申请号：US11059475

申请日：2005-02-16

申请人： Der-Tsyr Fan ,  Jung-Chang Lu ,  Chiou-Feng Chen ,  Prateep Tuntasood

发明人： Der-Tsyr Fan ,  Jung-Chang Lu ,  Chiou-Feng Chen ,  Prateep Tuntasood

IPC分类号： H01L29/336

CPC分类号： H01L27/115 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825

摘要： Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.

摘要翻译： 闪存和制造过程，其中在堆叠的，自对准的浮动和控制栅极之间的沟槽中用选择栅极形成存储器单元，其中由选择栅极选通的掩埋的源极和漏极区域。 擦除路径形成在浮动栅极和选择栅极的突出的圆形边缘之间，并且编程路径从选择栅极之间的中间沟道区域和通过栅极氧化物的浮动栅极延伸到浮动栅极的边缘。 根据阵列结构，可以在浮动和控制栅极的一侧或两侧设置倾斜的选择栅极，并且在蚀刻衬底和其它材料以形成沟槽时将堆叠的栅极和覆盖它们的电介质用作自对准掩模 。

公开(公告)号：US06885586B2

公开(公告)日：2005-04-26

申请号：US10251664

申请日：2002-09-19

申请人： Chiou-Feng Chen ,  Der-Tsyr Fan ,  Jung-Chang Lu ,  Prateep Tuntasood

发明人： Chiou-Feng Chen ,  Der-Tsyr Fan ,  Jung-Chang Lu ,  Prateep Tuntasood

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： Self-aligned split-gate NAND flash memory cell array and method of fabrication in which a series of self-aligned split cells are formed between a bit line diffusion and a common source diffusion. Each cell has control and floating gates which are stacked and self-aligned with each other, and a third gate which is split from but self-aligned with the other two. In some disclosed embodiments, the split gates are utilized as erase gates, and in others they are utilized as select gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

摘要翻译： 自对准分离栅极NAND闪存单元阵列及其制造方法，其中在位线扩散与公共源极扩散之间形成一系列自对准分裂单元。 每个单元具有彼此堆叠和自对准的控制和浮动栅极，以及与另外两个分离而自对准的第三栅极。 在一些公开的实施例中，分裂门用作擦除栅极，而在其它实施例中，它们被用作选择栅极。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

公开(公告)号：US07718488B2

公开(公告)日：2010-05-18

申请号：US11380595

申请日：2006-04-27

申请人： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

发明人： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115

摘要： Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

摘要翻译： 自对准分离栅闪存单元阵列和制造工艺，其中擦除和选择栅极位于堆叠的浮置和控制栅极的相对侧上，源极区在擦除栅极下方的衬底中，位线扩散部分重叠 通过在单元格行的末端的选择门。 浮置和控制栅极彼此自对准，并且擦除和选择栅极与堆叠栅极分离，但是自对准。 由于其他栅极和源极区域所围绕的浮动栅极，编程和擦除操作的高电压耦合显着增强。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

公开(公告)号：US20060203552A1

公开(公告)日：2006-09-14

申请号：US11380595

申请日：2006-04-27

申请人： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

发明人： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

IPC分类号： G11C16/04

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115

摘要： Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

摘要翻译： 自对准分离栅闪存单元阵列和制造工艺，其中擦除和选择栅极位于堆叠的浮置和控制栅极的相对侧上，源极区在擦除栅极下方的衬底中，位线扩散部分重叠 通过在单元格行的末端的选择门。 浮置和控制栅极彼此自对准，并且擦除和选择栅极与堆叠栅极分离，但是自对准。 由于其他栅极和源极区域所围绕的浮动栅极，编程和擦除操作的高电压耦合显着增强。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

公开(公告)号：US20050207225A1

公开(公告)日：2005-09-22

申请号：US10803183

申请日：2004-03-17

申请人： Chiou-Feng Chen ,  Caleb Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

发明人： Chiou-Feng Chen ,  Caleb Cho ,  Ming-Jer Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC分类号： G11C16/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC分类号： G11C16/0483 ,  G11C2216/04 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

摘要翻译： 自对准分裂栅极NAND闪速存储单元阵列及其制造工艺，其中自对准分裂栅极单元行在衬底的有源区域中的位线扩散与公共源极扩散之间形成。 每个单元具有彼此堆叠和自对准的控制和浮置栅极，并且擦除和选择与层叠栅极分离并与堆叠栅极自对准的栅极，每行的两端的选择栅极部分地重叠位 排列源扩散。 擦除栅极下面的沟道区域是重掺杂的，以减小位线和源极扩散之间的沟道电阻，并且浮置栅极以其它栅极包围，从而提供显着增强的与浮栅的高电压耦合 其他大门。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

公开(公告)号：US20050207199A1

公开(公告)日：2005-09-22

申请号：US10802253

申请日：2004-03-17

申请人： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

发明人： Chiou-Feng Chen ,  Prateep Tuntasood ,  Der-Tsyr Fan

IPC分类号： G11C5/02 ,  G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115

摘要： Self-aligned split-gate flash memory cell array and process of fabrication in which erase and select gates are positioned on opposite sides of stacked floating and control gates, with source regions in the substrate beneath the erase gates, bit line diffusions which are partially overlapped by select gates at the ends of the rows of the cells. The floating and control gates are self-aligned with each other, and the erase and select gates are split from but self-aligned with the stacked gates. With the floating gates surrounded by the other gates and the source regions, high voltage coupling for both programming and erase operations is significantly enhanced. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.

摘要翻译： 自对准分离栅闪存单元阵列和制造工艺，其中擦除和选择栅极位于堆叠的浮置和控制栅极的相对侧上，源极区在擦除栅极下方的衬底中，位线扩散部分重叠 通过在单元格行的末端的选择门。 浮置和控制栅极彼此自对准，并且擦除和选择栅极与堆叠栅极分离，但是自对准。 由于其他栅极和源极区域所围绕的浮动栅极，编程和擦除操作的高电压耦合显着增强。 存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

公开(公告)号：US07646641B2

公开(公告)日：2010-01-12

申请号：US10869475

申请日：2004-06-15

申请人： Chiou-Feng Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

发明人： Chiou-Feng Chen ,  Der-Tsyr Fan ,  Prateep Tuntasood

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11568

摘要： NAND flash memory cell array having control gates and charge storage gates stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion, with select gates on both sides of each of the pairs of stacked gates. The gates in each stacked pair are self-aligned with each other, and the charge storage gates are either a nitride or a combination of nitride and oxide. Programming is done by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates. Erasing is done by channel tunneling from the charge storage gates to the silicon substrate or by hot hole injection from the silicon substrate to the charge storage gates. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

摘要翻译： NAND闪速存储单元阵列具有控制栅极和电荷存储门，它们成对地排列成位线扩散和公共源极扩散之间的行，每对堆叠栅极的两侧具有选择栅极。 每个堆叠对中的栅极彼此自对准，并且电荷存储栅极是氮化物或氮化物和氧化物的组合。 通过从硅衬底到电荷存储门的热电子注入来完成编程，以在电荷存储门中建立负电荷。 通过从电荷存储栅极到硅衬底的沟道隧穿或通过从硅衬底到电荷存储栅的热空穴注入来完成擦除。 该阵列被偏置，使得所有的存储单元可以同时被擦除，而编程是位可选择的。